Variable Resistance Memory Bottom Contact Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional variable resistance memory elements require large operating currents, leading to high power consumption, and there is a need to reduce current requirements while maintaining the ability to heat the variable resistance material past its melting point and quench it in an amorphous state.
Innovation Solution
The development of a variable resistance memory element with a sub 1000 nm2 bottom contact area, which reduces the reset current requirement and write transistor size, achieved by optimizing the contact area uniformity and using a phase change material like GST, with a small bottom electrode configuration that maximizes current density at the interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional variable resistance memory element uses a larger bottom contact area, then it can maintain sufficient current density for heating the phase change material, but it results in high power consumption and large reset current requirements
Solution Approach 1:
The patent applies local quality by creating a non-uniform bottom electrode structure where the contact area varies spatially. Specifically, the bottom electrode has a smaller contact area at the center region (where current density is needed) compared to the peripheral regions. This localized variation in contact area allows the device to achieve high current density at the phase change material interface for effective heating, while the overall smaller effective contact area reduces the total reset current requirement and power consumption.
2Power
If the bottom contact area is reduced to lower reset current requirements, then power consumption decreases, but it becomes difficult to heat the variable resistance material past its melting point
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through a spatially varying bottom electrode contact area. The center region has a smaller contact area to reduce overall power consumption and reset current requirements, while the peripheral regions extend further to provide sufficient current pathways. This configuration concentrates current density at the phase change material interface where needed for heating, while the total effective contact area remains small enough to reduce the reset current requirement below conventional levels.
3Device complexity
If the bottom electrode contact area is made smaller, then the write transistor size can be reduced, but the current density uniformity across the contact area becomes more difficult to maintain
Solution Approach 1:
The patent applies asymmetry by designing a bottom electrode with an annular or ring-shaped contact area rather than a symmetric circular or square contact. The bottom electrode has an inner radius and an outer radius, creating an asymmetric annular region that provides uniform current distribution. This asymmetric geometry naturally promotes uniform current density across the contact area while maintaining a small effective area, thereby reducing write transistor size without sacrificing current uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a phase change memory element with reduced power consumption and lower reset current requirements, maintaining high current density to heat and quench the phase change material effectively, thereby reducing overall power usage.
Implementation Method 1
phase change materials such as chalcogenide alloys, which are capable of stably transitioning between amorphous and crystalline phases
Implementation Method 2
heating and cooling of the GST material can occur by causing differing amplitudes of current to flow through the GST material
Data Source
AI summary
A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.