Variable Resistance Memory Cell With Dual Elements
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Solution Overview
Problem
Current memory circuits face limitations in read and write operation margins and speeds due to the lack of effective integration of variable resistance elements, leading to reduced reliability and increased power consumption.
Innovation Solution
The proposed electronic device incorporates semiconductor memory units with storage cells featuring two variable resistance elements, where the resistance values are switched based on current directions, enabling improved read and write operations through the use of driving blocks that latch data based on current flow, thereby enhancing the integration and efficiency of storage cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory circuits with single variable resistance element are used, then device complexity is reduced, but read and write operation margins and speeds deteriorate
Solution Approach 1:
The storage cell is segmented into two separate variable resistance elements (first VRE and second VRE) instead of using a single element. Each VRE independently stores one bit of data, allowing parallel read/write operations and improving operation speed and margin while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent transitions from a single-dimension storage approach (one VRE) to a two-dimension approach (two VREs arranged in specific configurations with separate bit lines and word lines). This dimensional expansion enables independent control and reading of multiple storage elements, significantly improving read/write margins and speeds
2Reliability
If storage cells with two variable resistance elements are implemented, then read and write operation margins increase, but manufacturing complexity increases
Solution Approach 1:
The patent merges two variable resistance elements into a single storage cell unit with integrated bit lines, word lines, and selection transistors. This unified structure improves read/write margins through differential signaling while simplifying manufacturing by treating the dual-VRE cell as a standardized module that can be replicated across the memory array
Solution Approach 2:
The storage cell design with two VREs serves multiple functions simultaneously: data storage, differential signaling for improved margin, and parallel operation capability. This multi-functional approach enhances reliability without proportionally increasing manufacturing complexity, as the same structural elements serve multiple purposes
3Loss of energy
If conventional storage cells are used, then device size is reduced, but power consumption increases
Solution Approach 1:
The dual variable resistance element structure enables self-service through differential read operations where one VRE acts as a reference to the other. This differential approach improves power efficiency by eliminating the need for separate reference cells, reducing overall power consumption while the compact arrangement of the two VREs minimizes the increase in device volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the margins and speeds of read and write operations, reduces power consumption, and decreases the size of electronic devices by increasing the degree of integration of storage cells with two variable resistance elements.
Implementation Method 1
each storage cell including a first variable resistance element which has a first resistance value when a first value is stored therein and a second resistance value when a second value is stored therein and a second variable resistance element which has the second resistance value when the first value is stored therein and the first resistance value when the second value is stored therein
Implementation Method 2
the driving block further configured to, in a read operation, latch data corresponding to a current flowing through the bit line and the bit line bar
Data Source
AI summary
Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.