Variable Resistance Memory Cells for Analog Synaptic Weight Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices, particularly those in neural networks, face challenges in mimicking neuro-biological architectures and efficiently storing synaptic weights, which are crucial for learning and biological functions, due to limitations in traditional computer architectures.
Innovation Solution
The use of an array of variable resistance memory cells and a neural memory unit controller that applies sub-threshold voltage pulses to change the threshold voltage of memory cells in an analog fashion, allowing for incremental synaptic weight changes, thereby mimicking neuro-biological functionalities like learning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional memory devices are used, then storage capacity is provided, but the ability to mimic neuro-biological architectures and store synaptic weights is limited
Solution Approach 1:
The patent utilizes variable resistance memory cells where the resistance state (high or low) represents different synaptic weight values. By changing the resistance parameter of the memory cell, the system can store and represent continuous or discrete synaptic weight values, enabling neuro-biological functionality. This parameter change approach allows the memory device to adapt to different storage requirements and mimic biological synapses.
2Adaptability or versatility
If variable resistance memory cells are used, then synaptic weight storage is enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-selecting memory cells that can autonomously select themselves during read operations without requiring additional selection transistors. The memory cell automatically activates when the appropriate voltage threshold is reached, eliminating the need for external selection mechanisms and reducing manufacturing complexity. This self-service capability simplifies the cross-point array structure and reduces precision requirements for external control circuits.
Solution Approach 2:
The variable resistance memory cell serves multiple functions: it acts as both the storage element and the selection element. The same cell that stores the synaptic weight also performs the selection function during read operations, eliminating the need for separate selection components. This multi-functionality reduces the overall device complexity and manufacturing precision requirements.
3Quantity of substance
If cross-point architecture is used, then memory cell density is improved, but access control complexity increases
Solution Approach 1:
In the cross-point architecture, each memory cell is self-selecting, meaning it automatically activates when the voltage threshold corresponding to its stored value is applied. This eliminates the need for complex external selection circuits for each cell, as the cells themselves perform the selection function. The access control is simplified to applying voltage thresholds along the bit lines, which automatically selects the appropriate memory cells without requiring additional control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables memory devices to effectively store and interpret synaptic weights, facilitating learning and other biological functions by allowing for incremental and analog changes in threshold voltages, enhancing the capabilities of neural network memory systems.
Implementation Method 1
Some memory cells can be, for example, resistance variable memory cells whose logic state (e.g., stored data value) depends on the programmed resistance of the memory cell
Data Source
AI summary
In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a variable resistance memory cell of the array to change a threshold voltage of the variable resistance memory cell in an analog fashion from a voltage associated with a reset state to effectuate a first synaptic weight change; and apply additional sub-threshold voltage pulses to the variable resistance memory cell to effectuate each subsequent synaptic weight change.