Variable Resistance Memory with Dual Decoder Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face challenges in ensuring the certainty of state changes during forming, setting, and resetting operations in variable resistance elements, which affects the reliability and efficiency of data storage.
Innovation Solution
A nonvolatile semiconductor memory device configuration that includes a memory cell array with variable resistance elements, multiple decoders for line selection, and a voltage application circuit to apply specific voltages for forming, setting, and resetting operations, utilizing a dual-row and dual-column control circuit architecture to optimize wiring resistance and reduce operational load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage is applied to the variable resistance element for forming, setting, or resetting operations, then the state of the variable resistance element changes, but the certainty of state change is insufficient
Solution Approach 1:
The control circuit is segmented into dual row decoders and dual column decoders, allowing independent control of row and column lines. This segmentation enables precise voltage application to specific memory cells while providing protective wiring resistance through the decoder structure, improving state change certainty without excessive complexity
Solution Approach 2:
The patent applies different resistance characteristics to different parts of the circuit. The wiring resistance in the row and column lines is utilized as a protective element specifically during forming operations, while other parts of the circuit maintain low resistance for efficient data operations. This local differentiation improves reliability without compromising overall performance
2Productivity
If wiring resistance is utilized as a protective element during forming, then the yield and number of write times improve, but the device complexity increases
Solution Approach 1:
The wiring resistance in the row and column lines, which would normally be considered a parasitic effect, is made to serve a useful function as a protective element during forming operations. The existing wiring structure provides the necessary resistance without requiring additional protective components, improving productivity while avoiding excessive complexity
Solution Approach 2:
The row and column lines serve multiple functions: they provide signal routing for data operations and simultaneously provide protective resistance during forming operations. This multi-functionality allows the same circuit structure to improve both data operation efficiency and forming reliability without adding separate protective circuitry
3Productivity
If a certain voltage is applied to change the variable resistance element from high-resistance state to low-resistance state during setting operation, then data is written, but load on the memory cell increases
Solution Approach 1:
The row and column decoders act as intermediary elements between the control circuit and the memory cell. During setting operations, the decoders provide protective resistance that limits the current and voltage stress on the memory cell, reducing load while still enabling successful data writing. This intermediary function protects the memory cell from excessive stress
4Productivity
If voltage is applied during resetting operation to change from low-resistance state to high-resistance state, then data is erased, but IR drop affects operational reliability
Solution Approach 1:
Instead of trying to minimize wiring resistance to reduce IR drop, the patent inverts the approach by utilizing the wiring resistance as a beneficial protective element. The dual-row and dual-column decoder structure ensures that the wiring resistance provides appropriate current limiting during resetting operations, improving operational reliability while maintaining data erase capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the yield and number of write times for memory cells by utilizing wiring resistance as a protective element during forming and reducing load during setting, while minimizing IR drop during resetting, thereby enhancing the reliability and efficiency of data storage operations.
Implementation Method 1
a variable resistance element configured to store an electrically rewritable resistance value as data in a nonvolatile manner
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.