Variable Resistance Memory Device with Recessed Patterns
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Solution Overview
Problem
Conventional non-volatile memory devices experience malfunctions due to charge interference between adjacent cells and require high operation voltages, leading to larger device sizes and inefficiencies.
Innovation Solution
A non-volatile memory device with recesses in a semiconductor substrate filled with variable resistance patterns, where impurity regions define a channel region, allowing for low-voltage operation by changing resistance patterns to program, erase, and read data, reducing cell interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate-type or charge trap-type memory devices are used, then data can be stored by charging/discharging electrons, but charge interference between adjacent cells causes malfunctions
Solution Approach 1:
The memory device is divided into isolated cell units with individual tunnel oxide layers and charge trapping layers. Each cell is electrically isolated by insulating layers and physical separation, preventing charge interference between adjacent cells while maintaining independent charge storage capability for reliable data storage.
Solution Approach 2:
A tunnel oxide layer is introduced as an intermediary barrier between the semiconductor substrate and the charge trapping layer. This intermediate layer enables controlled charge injection during programming while blocking charge leakage and interference, thereby improving reliability without requiring high operation voltages.
2Ease of manufacture
If NOR-type memory devices use hot carrier injection for programming, then data can be programmed, but punch-through effects occur between source and drain regions
Solution Approach 1:
The conventional hot carrier injection mechanism is replaced with a field-effect-based programming approach. High electric fields are applied across the tunnel oxide layer to enable charge tunneling, eliminating the need for high-current flow through source-drain regions and preventing punch-through effects while maintaining programming capability.
Solution Approach 2:
The programming mechanism transitions from hot carrier injection requiring high currents to field-effect charge tunneling using controlled electric fields. This parameter change in the programming approach eliminates punch-through effects between source and drain regions while achieving reliable data programming.
3Ease of operation
If high voltage of about 10V is applied to NOR-type memory devices, then operation is enabled, but high voltage transistors increase device size
Solution Approach 1:
The operation voltage is reduced from conventional high voltages (about 10V) to lower voltages by utilizing field-effect charge tunneling mechanisms. The tunnel oxide layer thickness and material composition are optimized to enable effective charge injection and retrieval at reduced voltages, eliminating the need for large high-voltage transistors and reducing overall device size.
Solution Approach 2:
The memory device structure transitions from planar two-dimensional layout to a vertically-stacked three-dimensional configuration with multiple layers (semiconductor substrate, tunnel oxide layer, charge trapping layer, blocking layer, electrode). This vertical stacking enables higher integration density and smaller device footprint while maintaining operation at lower voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes cell interference and operates at lower voltages, enhancing the reliability and integration of non-volatile memory devices while eliminating the need for high-voltage transistors, resulting in a more compact and efficient memory device.
Implementation Method 1
The resistance patterns may include a material having a resistance that is variable in accordance with a voltage applied thereto
Implementation Method 2
First and second impurity regions may be formed at a surface of the substrate. The first and second impurity regions may contact side surfaces of the resistance patterns to define a channel region between the resistance patterns
Data Source
AI summary
A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.