Variable Resistance Memory Dummy Diode Leakage Reduction
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Solution Overview
Problem
Leakage currents from memory cells in the dummy region of a nonvolatile variable resistive memory device can affect the operations of memory cells in the cell region, necessitating a method to reduce these currents and ensure stable device performance.
Innovation Solution
The method involves forming memory devices with a dummy region that includes a diode with a lightly doped impurity layer to reduce leakage currents, where the impurity layers in the dummy diode have a lower concentration of impurities compared to the cell diode, thereby electrically isolating the dummy region from the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy region is added around the cell region to improve device performance, then reliability is improved, but leakage currents from dummy diodes affect cell region operations
Solution Approach 1:
The patent applies local quality by creating asymmetric doping concentrations specifically in the dummy region diodes. The first impurity layer in dummy diodes is doped at a lower concentration than in cell diodes, while the second impurity layer maintains the same doping concentration. This localized modification reduces leakage currents from dummy diodes without affecting cell diode performance, as each region receives tailored doping treatment according to its specific functional requirements.
2Object-generated harmful factors
If impurity concentration in dummy diode is reduced to minimize leakage currents, then harmful factors are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the doping process into two distinct impurity layers with different doping strategies. The first impurity layer is doped at different concentrations for dummy versus cell regions, while the second impurity layer is doped uniformly. This segmentation allows independent optimization of each layer's doping concentration, reducing the need for precise simultaneous control of multiple parameters and simplifying the manufacturing process.
Solution Approach 2:
The patent applies partial action by modifying only the first impurity layer's doping concentration in the dummy region, while leaving the second impurity layer unchanged. This selective modification achieves the goal of reducing leakage currents without requiring comprehensive changes to the entire doping process, thereby reducing manufacturing complexity and precision requirements.
3Reliability
If dummy region is electrically isolated from cell region to prevent interference, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent achieves electrical isolation by changing the doping concentration parameter of the first impurity layer in dummy diodes. By lowering the doping concentration, the depletion region width increases, creating natural electrical isolation between the dummy and cell regions. This parameter-based isolation method avoids the need for additional physical isolation structures, maintaining device simplicity while achieving the desired electrical separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage currents from the dummy diodes, ensuring stable and precise operations of the memory device by minimizing the impact of dummy region operations on the cell region, thereby enhancing the overall performance and reliability of the memory device.
Implementation Method 1
the impurity layers in the dummy diode have a lower concentration of impurities compared to the cell diode, thereby electrically isolating the dummy region from the cell region
Data Source
AI summary
A method of fabricating a memory device includes defining a cell region on a substrate and defining a dummy region around the cell region, forming bit lines on a top surface of the substrate, the bit lines extending in one direction, forming cell vertical structures on top surfaces of the bit lines corresponding to the cell region, each cell vertical structure including a cell diode and a variable resistive element, forming dummy vertical structures on top surfaces of the bit lines corresponding to the dummy region, each dummy vertical structure including a dummy diode and a variable resistive element, and forming word lines in contact with top surfaces of the cell vertical structures and dummy vertical structures, the word lines intersecting the bit lines at right angles. The cell diode includes a first impurity pattern and a second impurity pattern, the dummy diode includes a first lightly doped impurity pattern and a second impurity pattern, and the variable resistive element includes a first electrode, a variable resistor, and a second electrode.