Variable Resistance Memory Fault Detection via Unidirectional Diodes

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional 1D1R cross point nonvolatile memory devices face issues with faulty memory cells due to leakage currents, making it difficult to detect and correct faults, especially with bidirectional current steering elements, which leads to unstable operation and increased memory cell faults as capacity increases.

Innovation Solution

A variable resistance nonvolatile memory device with a memory cell array featuring a variable resistance element and a current steering element at three-dimensional cross points, utilizing a selection circuit to select memory cells, a write circuit to set resistance states, and a read circuit to detect faulty cells by applying specific voltage pulses and determining current thresholds, allowing for reliable operation and fault correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If bidirectional current steering elements are used in 1D1R cross point memory cells, then the memory device can achieve higher integration density and smaller cell area, but leakage current faults cannot be detected and the operation becomes unstable

Engineering Contradiction:
Improvecell area sizeVSAvoidoperation stability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent introduces asymmetry by using unidirectional current steering elements (diodes) instead of bidirectional elements. This asymmetric current flow characteristic allows the diode to conduct current in only one direction, enabling fault detection through differential voltage application. The unidirectional property creates distinguishable electrical characteristics between normal and faulty cells, resolving the reliability issue while maintaining the compact 1D1R cross point structure.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent implements preliminary fault detection by applying a specific voltage pattern before normal read operations. A first voltage is applied to detect leakage currents in faulty memory cells, allowing the system to identify and handle defective cells proactively. This preliminary detection mechanism prevents unstable operation during subsequent read/write cycles, ensuring reliable performance.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If memory cell array capacity is increased, then the storage density and capacity of the memory device are improved, but the number of memory cell faults increases

Engineering Contradiction:
Improvememory cell capacityVSAvoidfault rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the read circuit detects current flow patterns to identify faulty memory cells. When a leakage current is detected in a faulty cell, the system generates feedback signals to prevent access to that cell or to trigger error correction procedures. This feedback loop allows the memory device to maintain high capacity while actively managing and compensating for faults that increase with array size.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The memory device performs self-diagnosis through built-in fault detection circuitry that automatically identifies defective cells during operation. The system uses the electrical characteristics of the memory cells themselves to detect faults without requiring external testing equipment. This self-service capability enables the device to maintain reliability despite increasing capacity and associated fault rates.

Inventive Principle:
Principle #25Self-service

3Device complexity

If conventional fault detection methods are used with bidirectional current steering elements, then the detection process is simple, but faulty memory cells cannot be accurately identified due to leakage currents

Engineering Contradiction:
Improvedetection process complexityVSAvoidfault detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent uses the asymmetric conduction特性 of unidirectional diodes to improve fault detection accuracy. By applying voltages in different polarities and observing current flow patterns, the system can distinguish between normal resistance variations and actual leakage faults. The unidirectional diode's inherent asymmetry creates distinct electrical signatures for faulty versus normal cells, enabling accurate detection without significantly increasing system complexity.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables a highly reliable and stable operation of the nonvolatile memory device by accurately identifying and rescuing faulty memory cells, preventing leakage currents and maintaining performance even as capacity increases.

Implementation Method 1

a variable resistance element that reversibly changes, in response to the application of a voltage pulse, between a low resistance state and a high resistance state

Methodology Applied
Scientific EffectVariable resistance effect: Electrical Resistance

Implementation Method 2

a current steering element typified by a diode element... the current steering element carrying a current from which the current steering element is assumed to be conducting as a result of an application of a voltage exceeding a predetermined threshold voltage

Methodology Applied
Scientific EffectDiode conduction effect: Diode

Data Source

PatentUS8848422B2Variable resistance nonvolatile memory device and driving method thereof
Publication Date: 2014.09.30 PANASONIC SEMICON SOLUTIONS CO LTD
  • US8848422B2 patent drawing
  • US8848422B2 patent drawing
  • US8848422B2 patent drawing

AI summary

A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.