Variable Resistance Memory Fault Isolation via Detection Circuit
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Solution Overview
Problem
Conventional 1D1R cross point type nonvolatile memory devices face issues with leakage current problems, leading to unstable operations due to faulty memory cells, where a faulty diode element causes misidentification of memory cells and prevents stable reading, and existing fault detection methods cannot accurately identify the faulty cell or prevent sneak current in bidirectional arrays.
Innovation Solution
A variable resistance nonvolatile memory device with a memory cell array featuring a variable resistance element and a current steering element connected in series at three-dimensional cross points, along with a detection circuit that identifies faulty memory cells in a second low resistance state and sets the connected bit and word lines to an inactive state to reduce abnormal currents and ensure stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a diode element is used as a current steering element in a 1D1R cross point type memory cell, then the device complexity is reduced compared to using a transistor, but leakage current increases leading to unstable operation
Solution Approach 1:
The patent implements a detection circuit that performs preliminary detection of faulty memory cells before normal read/write operations. The detection circuit applies a detection voltage to identify cells with leakage current exceeding a threshold, and the control circuit preemptively sets faulty cells to an inactive state, preventing them from causing operational instability during subsequent memory operations.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the detection circuit and the memory cell array. This control circuit receives detection results and automatically manages the state of memory cells by setting faulty cells to an inactive state, thereby mediating the impact of leakage current on overall system stability without requiring complex circuit redesign.
2Measurement precision
If fault detection is performed using conventional methods in bidirectional memory cell arrays, then faulty cells can be identified, but sneak current cannot be prevented leading to continued operational issues
Solution Approach 1:
The patent converts the harmful effect of sneak current and leakage current into a useful detection mechanism. By monitoring the current flowing through memory cells during detection operations, the system identifies faulty cells that generate abnormal current, and then isolates them by setting them to an inactive state, thereby transforming the harmful current into a diagnostic signal.
Solution Approach 2:
The patent implements dynamic state management where memory cells can transition between active and inactive states based on their health status. The control circuit dynamically adjusts the state of each memory cell row or column based on detection results, allowing the system to adapt to faults in real-time and maintain stable operation despite the presence of faulty cells in the array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables stable operation of the memory device by reducing abnormal currents and accurately identifying and isolating faulty memory cells, thereby preventing misidentification and sneak currents, ensuring reliable data storage and retrieval.
Implementation Method 1
a variable resistance element that reversibly changes, in response to the application of a voltage pulse, between a low resistance state and a high resistance state
Implementation Method 2
a current steering element typified by a diode element... the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied
Data Source
AI summary
A stable operation is implemented by reducing an abnormal current. A variable resistance nonvolatile memory device includes: a memory cell array having memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of bit lines and one of word lines, and the current steering element being assumed to be conducting when a voltage exceeding a predetermined threshold voltage is applied; and a detection circuit that detects a faulty memory cell that is in a second low resistance state where a resistance value is lower than a resistance value in a first low resistance state. Both the bit line and the word line that are connected to the faulty memory cell detected by the detection circuit are fixed in the inactive state.