Variable Resistance Memory Grid with Multi-Level Contacts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration with simple design and reliable fabrication processes, particularly in forming patterned structures with variable resistance elements like MRAM, where etching difficulties arise due to close intervals between elements.
Innovation Solution
The proposed solution involves forming semiconductor devices with variable resistance elements, such as MRAM, by creating a grid-like structure of active regions defined by isolation layers and word lines, where source and bit lines are formed at different heights, and contacts are alternately arranged to increase inter-pattern distance, facilitating easier patterning and reducing short-circuit risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If variable resistance elements are formed with close intervals to achieve high integration, then circuit element integration is improved, but etching difficulty increases and short-circuit risk increases
Solution Approach 1:
The patent introduces a third dimension by forming contacts at different heights (first contacts at a first height, second contacts at a second height). This vertical separation allows variable resistance elements to be arranged with close horizontal intervals for high integration while maintaining sufficient spacing through height differentiation, thereby enabling easier etching and reduced short-circuit risk without compromising integration density
2Productivity
If variable resistance elements are formed with close intervals to achieve high integration, then circuit element integration is improved, but short-circuit risk increases
Solution Approach 1:
The patent introduces a third dimension by forming contacts at different heights (first contacts at a first height, second contacts at a second height). This vertical separation allows variable resistance elements to be arranged with close horizontal intervals for high integration while maintaining sufficient spacing through height differentiation, thereby enabling easier etching and reduced short-circuit risk without compromising integration density
3Ease of manufacture
If contacts are alternately arranged at different heights, then inter-pattern distance is increased and patterning is simplified, but device structure becomes more complex
Solution Approach 1:
The patent segments the contact structure into multiple height levels, with first contacts formed at a first height and second contacts formed at a second height. This segmentation allows the patterning process to be simplified for each layer while the overall device achieves high integration, effectively distributing the structural complexity across multiple manageable segments rather than requiring a single complex pattern
Data Source
AI summary
A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit line contacts.