Variable Resistance Memory Cell Fabrication via Grooved Selection Layer
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Solution Overview
Problem
Current semiconductor devices face challenges in fabricating memory cells due to sidewall damage during etching processes and the complexity of forming inter-layer dielectric layers, which affects data storage and operating characteristics.
Innovation Solution
The semiconductor device incorporates a selection element layer with grooves where a variable resistance layer is buried, eliminating the need for an etch process for the variable resistance layer and reducing the complexity of forming inter-layer dielectric layers by using a spacer and conductive material layers to protect the selection element layer and prevent sidewall damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etch process is used to form the variable resistance layer, then the variable resistance layer can be formed with precise dimensions, but sidewall damage occurs during the etching process
Solution Approach 1:
The patent applies preliminary action by forming the selection element layer with grooves before forming the variable resistance layer. The grooves are pre-formed to guide the variable resistance layer material, eliminating the need for subsequent etching of the variable resistance layer itself. This preliminary structural preparation allows precise dimensional control without exposing the sidewalls to damaging etch processes.
Solution Approach 2:
The selection element layer acts as an intermediary structure that defines the shape and position of the variable resistance layer through its grooves. Instead of directly etching the variable resistance layer, the selection element layer's pre-formed grooves serve as a template or mediator, allowing the variable resistance layer to be deposited conformally without sidewall exposure to harmful etchants.
2Reliability
If inter-layer dielectric layers are formed between memory cells, then electrical isolation between cells is achieved, but the fabrication process becomes complex and time-consuming
Solution Approach 1:
The patent merges the functions of the selection element layer and the inter-layer dielectric by having the selection element layer's grooves directly surround and isolate the variable resistance layer. The selection element layer simultaneously provides electrical isolation (replacing the traditional inter-layer dielectric) and defines the memory cell structure, eliminating the need for separate dielectric deposition processes.
Solution Approach 2:
The selection element layer serves multiple functions: it provides electrical isolation between adjacent memory cells (traditionally the role of inter-layer dielectric), defines the geometric structure of the variable resistance layer through grooves, and contributes to the overall device architecture. This multi-functionality eliminates the need for separate inter-layer dielectric layers, simplifying the fabrication process.
3Manufacturing precision
If multiple deposition and etching steps are used to form memory cell layers, then precise layer structures are achieved, but the fabrication time and process complexity increase
Solution Approach 1:
The selection element layer with pre-formed grooves is created before depositing the variable resistance layer. This preliminary action establishes the exact shape and position of the variable resistance layer, allowing for precise layer structure formation in a single deposition step rather than requiring multiple deposition and etching cycles.
Solution Approach 2:
The patent extracts and eliminates unnecessary intermediate steps from the conventional fabrication process. By using the selection element layer's grooves to directly define the variable resistance layer structure, the method removes the need for intermediate etching steps that would otherwise be required to shape the variable resistance layer, reducing both process complexity and fabrication time.
Data Source
AI summary
An electronic device includes a semiconductor memory that includes: a first conductive pattern disposed over a substrate; a first selection element layer disposed over the first conductive pattern and having one or more first grooves therein, the first grooves overlapping the first conductive pattern; a first variable resistance layer whose sidewalls and bottom are surrounded by the first selection element layer, the first variable resistance layer being buried in the first groove; and a second conductive pattern that overlaps the first variable resistance layer and is disposed over the first variable resistance layer.