Variable Resistance Memory Hierarchical Signal Lines
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Solution Overview
Problem
Next-generation memory devices using variable resistance materials face challenges in increasing storage capacity and operating speed due to increased parasitic resistance and capacitance in signal lines, limiting their ability to perform high-speed operations.
Innovation Solution
A hierarchical layout of signal lines is developed for variable resistance memory cells, comprising a silicon substrate with uniformly separated active lines, switching devices, variable resistance devices, local and global bit lines, and word lines formed in different interconnection layers, optimizing the arrangement to enhance memory cell efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory chips is increased to increase storage capacity, then storage capacity is improved, but parasitic resistance and capacitance of signal lines increase, deteriorating operating speed
Solution Approach 1:
The patent segments the signal line system into multiple hierarchical levels (global bit lines, local bit lines, global word lines, local word lines) to divide the large memory chip into smaller functional blocks. This segmentation reduces the length of individual signal lines, thereby reducing parasitic resistance and capacitance while maintaining large storage capacity through the expanded memory array architecture.
Solution Approach 2:
The patent introduces a hierarchical structure that adds dimensional organization to the signal line layout. By creating multiple layers of signal lines (global and local levels) and organizing them in a systematic hierarchy, the patent reduces signal line interference and parasitic effects while accommodating increased storage capacity in a structured manner.
2Speed
If signal lines are formed in a hierarchical structure to reduce parasitic resistance and capacitance, then operating speed is improved, but device complexity increases
Solution Approach 1:
The complex signal line structure is segmented into standardized hierarchical units (global and local bit lines, global and local word lines) that can be systematically replicated and interconnected. This modular segmentation makes the complex structure more manageable and easier to manufacture despite the increased number of signal lines.
Solution Approach 2:
The hierarchical signal line structure uses universal patterns and repeated units that perform multiple functions. The same structural motifs are reused throughout the memory array, allowing the complex structure to be manufactured using standardized processes while achieving reduced parasitic effects through the hierarchical organization.
Data Source
AI summary
A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.