Variable Resistance Memory Device With High-K Dielectric Layer
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Solution Overview
Problem
Next-generation semiconductor memory devices require resistance change characteristics at low applied voltage with a wide resistance change range to achieve high integration and low power consumption, which existing technologies have not adequately addressed.
Innovation Solution
A variable resistance memory device is designed with a variable resistance layer comprising sequentially arranged first, second, and third oxide layers, where the second oxide layer has a higher dielectric constant than the first and third, allowing for a strong electric field to form and facilitate the formation of a conductive filament at a low applied voltage, enhancing resistance change performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional charge trap-based or phase change material-based devices are used, then resistance change can be achieved, but the device thickness is large and requires high applied voltage
Solution Approach 1:
The patent changes the material composition parameters of the variable resistance layer by incorporating multiple oxide layers with different dielectric constants (first oxide layer with dielectric constant κ1, second oxide layer with dielectric constant κ2 where κ2 > κ1, and third oxide layer with dielectric constant κ3 where κ3 ≥ κ1). This parameter change enables the formation of a strong internal electric field that facilitates conductive filament formation at lower applied voltages while maintaining a thin device structure
Solution Approach 2:
The patent employs a composite material structure consisting of sequentially arranged oxide layers with different dielectric properties. The variable resistance layer comprises a first oxide layer, a second oxide layer with higher dielectric constant, and a third oxide layer, creating a composite structure that generates enhanced internal electric fields to enable low-voltage operation and reduced thickness
2Reliability
If resistance change elements are designed for high integration and low power, then resistance change characteristics must occur at low applied voltage with wide resistance change range, but existing technologies have not adequately addressed this
Solution Approach 1:
The patent optimizes the dielectric constant parameters of the oxide layers to achieve reliable resistance change characteristics. By setting the second oxide layer's dielectric constant κ2 to be greater than the first oxide layer's dielectric constant κ1 (κ2 > κ1), and the third oxide layer's dielectric constant κ3 to be greater than or equal to κ1 (κ3 ≥ κ1), the structure generates sufficient internal electric field strength to ensure reliable conductive filament formation and rupture, achieving a wide resistance change range at low applied voltages
Solution Approach 2:
The patent applies local quality by creating regions with different dielectric constants within the variable resistance layer. The second oxide layer with higher dielectric constant (κ2 > κ1) is positioned between the first oxide layer (κ1) and third oxide layer (κ3 ≥ κ1), creating localized high-field regions that facilitate controlled conductive filament formation. This local variation in dielectric quality enables reliable resistance switching with reduced voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration enables a significant resistance change range with lower thickness than traditional charge trap-based or phase change material-based devices, achieving improved variable resistance performance and scalability for next-generation memory devices.
Implementation Method 1
A dielectric constant of the second oxide layer is greater than a dielectric constant of the first oxide layer and a dielectric constant of the third oxide layer
Data Source
AI summary
A variable resistance memory may include first and second conductive elements spaced apart from each other on a variable resistance layer. The variable resistance layer may include first to third oxide layers sequentially arranged in a direction perpendicular to a direction in which the first and second conductive elements are arranged. A dielectric constant of the second oxide layer may be greater than dielectric constants of the first and third oxide layers.