Variable Resistance Memory Hole Bottom Electrode Formation
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Solution Overview
Problem
The existing methods for manufacturing cross-point variable resistance nonvolatile storage devices face challenges in miniaturization due to the difficulty in forming metal electrodes only on the bottom of memory cell holes without electrical short circuits, which hinders the creation of high-aspect-ratio memory cells and large-capacity storage devices.
Innovation Solution
A method involving the formation of memory cell holes with a smaller opening diameter at the top than at the bottom, allowing for the deposition of a metal electrode layer only on the bottom and inner walls, preventing short circuits by using sputtering and specific insulating films to control the electrode placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal electrodes are formed in memory cell holes using conventional methods, then electrical connection is achieved, but electrical short circuits occur between lower and upper electrodes
Solution Approach 1:
The patent applies local quality by forming the metal electrode layer only on the bottom surface of the memory cell hole rather than uniformly on all surfaces. This is achieved by controlling the sputtering process to deposit metal selectively at the bottom, preventing electrical short circuits between lower and upper electrodes while ensuring reliable electrical connection where needed
2Productivity
If memory cell size is reduced for miniaturization, then storage capacity increases, but formation of metal electrodes without short circuits becomes difficult
Solution Approach 1:
The patent changes the parameters of the sputtering process, specifically controlling the deposition conditions to achieve selective metal layer formation on the bottom surface of memory cell holes. By adjusting sputtering parameters such as deposition rate, substrate temperature, and gas pressure, the metal is deposited only where needed, enabling precise electrode placement in miniaturized structures
Solution Approach 2:
The patent performs preliminary action by forming the metal electrode layer on the bottom surface of memory cell holes before forming the upper electrode. This sequence ensures that when the upper electrode is subsequently formed, no electrical short circuit can occur, as the lower electrode is already in place and protected by the insulating film structure
3Productivity
If high-aspect-ratio memory cells are formed, then device density increases, but conventional electrode formation methods fail to prevent short circuits
Solution Approach 1:
The patent applies local quality by restricting metal electrode layer formation to the bottom surface of high-aspect-ratio memory cell holes. This selective deposition ensures that even in tall, narrow holes where conventional methods would cause bridging, the metal is deposited only at the bottom, maintaining reliable electrode isolation throughout the structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reliable formation of metal electrodes as lower electrodes, preventing electrical conduction with upper electrodes and allowing for the creation of miniaturized, high-capacity variable resistance nonvolatile storage devices with embedded variable resistance elements.
Implementation Method 1
forming a metal electrode layer at least on a bottom of each of the plural memory cell holes by sputtering
Data Source
AI summary
Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole.