Variable Resistance Memory Cell Structure for High Integration
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Solution Overview
Problem
There is a demand for electronic devices with miniaturized, low power consumption, high performance, and multi-functionality that require improved memory storage capabilities, particularly in devices like computers and portable communication devices, where existing memory technologies struggle to enhance integration and reliability of variable resistance elements.
Innovation Solution
The development of semiconductor memory devices with a variable resistance layer structure that includes a first portion with variable resistance and a second portion without variable resistance, achieved by doping impurities to maintain or eliminate resistance characteristics, allowing for an 'all-around' structure that increases integration and simplifies fabrication, while maintaining reliable performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional variable resistance layer structure is used, then the memory cell horizontal area is larger, but the integration density is lower
Solution Approach 1:
The patent transitions from a planar variable resistance layer to a three-dimensional structure where the variable resistance layer is positioned within a hole formed in the interlayer dielectric layer. This vertical arrangement allows the memory cell to utilize the depth dimension, significantly reducing the horizontal footprint and increasing integration density while maintaining functional performance.
Solution Approach 2:
The variable resistance layer is nested within the hole structure, surrounded by the interlayer dielectric layer on multiple sides. This nested configuration allows efficient use of space by placing the active variable resistance element within the void space created by the contact hole, thereby maximizing the use of available volume and reducing the overall cell area.
2Reliability
If a complex variable resistance layer structure is used, then the data storage characteristics are improved, but the fabrication process becomes more difficult
Solution Approach 1:
The variable resistance layer is segmented into a first portion and a second portion with different impurity concentrations. The first portion (with lower impurity concentration) provides the primary variable resistance effect for data storage, while the second portion (with higher impurity concentration) provides structural support and electrical contact. This segmentation allows each portion to be optimized independently, improving data storage characteristics while maintaining fabrication simplicity through selective doping regions.
Solution Approach 2:
Different regions of the variable resistance layer are doped with different impurity concentrations to create local quality variations. The first portion has lower impurity concentration for optimal variable resistance characteristics, while the second portion has higher impurity concentration for structural stability and electrical conductivity. This local quality approach enhances data storage performance without requiring complex overall structure design.
3Device complexity
If impurities are added to the variable resistance layer, then the variable resistance characteristic is lost in certain regions, but this enables the all-around structure
Solution Approach 1:
Impurities are selectively added to specific regions (the second portion) of the variable resistance layer to create local quality differences. The first portion maintains low impurity concentration to preserve variable resistance characteristics for data storage, while the second portion receives higher impurity concentration to provide structural support and electrical contact functionality. This localized impurity addition enables the all-around structure without compromising the variable resistance effect in the active region.
Solution Approach 2:
The variable resistance layer is divided into functional segments: the first portion remains relatively pure to maintain variable resistance for data storage, while the second portion is doped with impurities to provide structural and electrical support. This segmentation allows the structure to achieve the all-around configuration with impurity-doped regions for mechanical stability while preserving the essential variable resistance characteristic in the undoped or lightly-doped first portion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and reliability of variable resistance elements, reduces the horizontal area required for memory cells, simplifies the fabrication process, and improves data storage characteristics, leading to more efficient and compact electronic devices.
Implementation Method 1
a variable resistance layer formed over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance
Implementation Method 2
the second portion includes impurities which cause a loss of the variable resistance
Implementation Method 3
the variable resistance layer includes a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction
Implementation Method 4
a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer
Data Source
AI summary
The disclosed technology provides an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.