Variable Resistance Memory Fabrication via Intersecting Stacked Structures
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Solution Overview
Problem
The existing methods for fabricating variable resistance memory devices with cross point cell array structures face issues such as misalignment between top and bottom layers, leading to increased contact resistance and complex, costly fabrication processes due to the need for separate patterning of electrodes and variable resistance patterns.
Innovation Solution
A method involving sequential formation of conductive and variable resistance layers, followed by selective etching and insulating layer deposition to create stacked structures, with mask patterns forming lines that intersect, simplifying the process and reducing misalignment-related defects and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate patterning processes are used for bottom electrodes, memory cells, and top electrodes, then each layer can be formed independently, but misalignment between layers occurs and contact resistance increases
Solution Approach 1:
The patent combines the patterning of bottom electrodes, memory cells, and top electrodes into a single mask process. The mask pattern simultaneously defines all three structures, ensuring perfect alignment between layers and eliminating misalignment-induced contact resistance while reducing the number of fabrication steps.
Solution Approach 2:
The patent introduces a vertical stacked structure where bottom electrodes, memory cells, and top electrodes are arranged in the thickness direction. This three-dimensional configuration allows all components to be formed through a single planar mask process, transforming a multi-step lateral patterning problem into a single-step vertical stacking solution.
2Ease of manufacture
If multiple separate mask processes are repeated for fabricating stacked structures, then each layer can be precisely formed, but the fabrication process becomes complicated and costs increase
Solution Approach 1:
The patent merges multiple mask processes into a single integrated masking step. The unified mask pattern concurrently defines bottom electrodes, memory cell regions, and top electrode positions, simplifying the fabrication process while maintaining precise layer formation through the vertical stacked architecture.
3Reliability
If bottom electrodes, memory cells, and top electrodes are formed by separate patterning, then each component can be optimized independently, but contact resistance suddenly increases due to misalignment
Solution Approach 1:
The patent combines the patterning of all electrode and memory cell structures into a single mask process, ensuring perfect spatial alignment between bottom electrodes, memory cells, and top electrodes. This eliminates misalignment-induced contact resistance and improves device reliability while reducing process complexity.
Data Source
AI summary
A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.