Variable Resistance Memory With Localized Ion Implantation Barriers
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved characteristics for variable resistance elements, particularly in memory circuits, due to limitations in manufacturing processes that affect the density and distribution of buried gates and ion implantation barriers, leading to issues with threshold voltage control and resistance state switching.
Innovation Solution
The method involves forming buried gates with different density distributions in distinct regions of a substrate, using an ion implantation barrier layer to control ion implantation depth, and integrating a variable resistance element connected to these gates, which includes materials like transition metal oxides and phase-change materials to switch between resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implantation is performed uniformly across the substrate, then the manufacturing process is simple, but the threshold voltage control and resistance state switching characteristics deteriorate
Solution Approach 1:
The patent applies local quality by forming an ion implantation barrier layer selectively in the peripheral region but not in the cell region. This allows different ion implantation characteristics in different areas: the cell region receives full ion implantation for proper threshold voltage control, while the peripheral region has restricted ion implantation to prevent excessive dopant accumulation. The barrier layer is removed only where needed, creating spatially varying implantation depth and concentration that satisfies both manufacturing simplicity and precision requirements.
2Quantity of substance
If the distance between adjacent buried gates is reduced to increase density, then the device integration density improves, but the ion implantation control and junction formation precision deteriorate
Solution Approach 1:
The patent addresses this contradiction by applying local quality through region-specific barrier layer formation. In the cell region where small gate spacing is critical for density, no barrier layer is formed, allowing ions to reach the intended junction depth. In the peripheral region where larger spacing exists and precise junction control is needed, the barrier layer prevents excessive ion penetration. This spatial differentiation allows high gate density in the cell region while maintaining junction precision in the peripheral region.
3Stability of the object's composition
If ion implantation barrier layer is formed in all regions, then the dopant distribution is uniform, but the threshold voltage control and resistance switching characteristics in the cell region deteriorate
Solution Approach 1:
The patent resolves this contradiction by applying local quality through selective barrier layer formation. The barrier layer is formed only in the peripheral region, allowing uniform dopant distribution where needed for stable transistor operation. In the cell region, the absence of the barrier layer enables the specific dopant distribution required for proper threshold voltage control and variable resistance element characteristics. This spatially selective approach maintains both dopant uniformity in peripheral regions and characteristic reliability in cell regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of semiconductor memory devices by improving the characteristics of variable resistance elements, enabling effective threshold voltage control and reliable resistance state switching, thus improving the operating characteristics of memory circuits.
Implementation Method 1
forming a junction by performing ion implantation into the substrate between the adjacent buried gates in the first and second regions
Data Source
AI summary
An electronic device may include a semiconductor memory. The semiconductor memory may include a substrate including a first region and a second region; buried gates formed in the first region and the second region, the buried gates in the second region having a different density distribution from the buried gates in the first region; first and second junction regions formed in the first and second regions, respectively, and having a same depth as each other; and a variable resistance element formed over the substrate and electrically connected to the buried gates in the first region. According to the implementations, the characteristics of the variable resistance element can be improved.