Variable Resistance Memory Layers for Multi-Bit Data Storage

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving improved operational characteristics and reliability, particularly in miniaturized electronic devices that require low power consumption and high performance, as they struggle to efficiently store multi-bit data due to limitations in crystallization speeds and doping element effects.

Innovation Solution

The proposed electronic device incorporates a semiconductor memory with multiple variable resistance layers, including antimony (Sb) with varying contents and crystallization speeds, and electrodes, allowing for differential set operation speeds, and employs doping elements to control crystallization, enabling efficient storage of multi-bit data through precise control of crystallization states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single variable resistance layer is used, then the device structure is simple, but the ability to store multi-bit data efficiently is limited

Engineering Contradiction:
ImprovestructureVSAvoiddata storage efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the single variable resistance layer into multiple variable resistance layers (first, second, and third layers) with different antimony contents and crystallization speeds. This segmentation allows each layer to be independently controlled during programming operations, enabling efficient storage of multi-bit data by selectively crystallizing different layers based on the data to be stored.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of control by varying the antimony content across different layers, which creates different crystallization speeds. This dimensional variation in material composition allows for differentiated programming currents to be applied to each layer, thereby enabling multi-bit data storage capability that overcomes the limitation of single-layer structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If high programming currents are used to achieve fast crystallization, then data processing speed is improved, but power consumption increases

Engineering Contradiction:
Improvedata processing speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by creating variable resistance layers with different antimony contents and crystallization characteristics at different positions. This allows each layer to be optimized for specific programming current levels, enabling fast crystallization in some layers with lower currents while maintaining overall data processing speed, thereby reducing total power consumption.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter (antimony content) across different layers to achieve different crystallization speeds. This parameter variation allows the system to achieve fast data processing by selectively crystallizing layers with appropriate crystallization speeds using optimized programming currents, reducing the energy required compared to using a single high-speed layer.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If antimony content is increased to improve crystallization speed, then programming efficiency is improved, but control precision over crystallization states deteriorates

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidcrystallization state control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the variable resistance function across multiple layers with different antimony contents. This segmentation allows each layer to operate in an optimized crystallization regime, where layers with higher antimony content provide fast crystallization for efficiency, while layers with lower antimony content provide precise control for setting specific resistance states, thereby maintaining both programming efficiency and control precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structures with varying antimony contents in different layers. This composite approach combines the advantages of high-antimony layers (fast crystallization) and low-antimony layers (precise state control), achieving both high programming efficiency and precise control over crystallization states through the synergistic combination of different material compositions.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the operational characteristics and reliability of the electronic device by allowing for reduced programming currents and voltages, enabling efficient storage of multi-bit data while improving data processing speed and functionality.

Implementation Method 1

a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer

Methodology Applied
Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS11283017B2Electronic device and operating method of electronic device
Publication Date: 2022.03.22 SK HYNIX INC
  • US11283017B2 patent drawing
  • US11283017B2 patent drawing
  • US11283017B2 patent drawing

AI summary

An electronic device may include a semiconductor memory. The semiconductor memory may include: a first variable resistance layer including antimony (Sb); a second variable resistance layer including antimony (Sb) with a content different from that of the first variable resistance layer, the second variable resistance layer having a crystallization speed different from that of the first variable resistance layer; and a first electrode interposed between the first variable resistance layer and the second variable resistance layer.