Variable Resistance Memory Device Layout Area Reduction
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Solution Overview
Problem
Conventional nonvolatile memory devices with crosspoint structures face challenges in high integration due to increased layout area and signal variations caused by capacitive coupling, leading to difficulties in wiring bit and word lines at minimum intervals without design margins.
Innovation Solution
A variable resistance nonvolatile memory device with a multi-layer stack structure, utilizing global bit lines and selection switch elements to connect bit lines in a hierarchical manner, ensuring that unselected bit lines adjacent to selected bit lines are disconnected from global bit lines, allowing for minimum wiring intervals without design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional nonvolatile memory devices with crosspoint structures are used, then memory cells can be placed at crosspoints of bit lines and word lines, but the layout area increases and high integration becomes difficult
Solution Approach 1:
The patent transitions from a planar crosspoint structure to a three-dimensional stacked structure where memory cells are formed between bit lines and word lines in different layers. This vertical stacking approach reduces the horizontal layout area while maintaining high integration density, effectively resolving the contradiction between area and integration productivity.
2Area of stationary object
If bit lines and word lines are wired at minimum intervals to reduce layout area, then area is reduced, but capacitive coupling increases causing signal variations
Solution Approach 1:
By stacking bit lines and word lines in multiple layers vertically, the patent reduces horizontal wiring intervals while maintaining sufficient vertical spacing between conductors. This three-dimensional arrangement minimizes capacitive coupling effects that would otherwise occur with tightly spaced planar wires, thereby maintaining signal stability while achieving compact layout.
Solution Approach 2:
The patent introduces selection switch elements as intermediary components between the memory cell array and global bit lines. These switches act as buffers that isolate unselected bit lines from global bit lines, preventing signal variations caused by capacitive coupling from propagating and affecting read operations, thus ensuring signal stability in compact layouts.
3Ease of operation
If unselected bit lines remain connected to global bit lines, then connectivity is maintained, but signal variations occur due to capacitive coupling with selected bit lines
Solution Approach 1:
The patent employs selection switch elements that dynamically change their connection state based on selection signals. During read operations, unselected bit lines are disconnected from global bit lines by controlling the selection switches, eliminating capacitive coupling interference. This dynamic switching maintains connectivity when needed while preventing signal variations during operations, resolving the contradiction between ease of operation and signal stability.
Data Source
AI summary
Each of basic array planes has a first via group that interconnects only even-layer bit lines in the basic array plane, and a second via group that interconnects only odd-layer bit lines in the basic array plane, the first via group in a first basic array plane and the second via group in a second basic array plane adjacent to the first basic array in a Y direction are adjacent to each other in the Y direction, and the second via group in the first basic array plane and the first via group in the second basic array plane are adjacent to each other in the Y direction, and the second via group in the second basic array plane is disconnected from a second global line when connecting the first via group in the first basic array plane to a first global line.