Variable Resistance Memory Devices With Merged Dummy Word Lines
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Solution Overview
Problem
Current integrated circuit memory devices face challenges in achieving high integration and reducing chip size due to the need for numerous selection transistors and complex wiring structures in variable resistance memory devices.
Innovation Solution
The implementation of a variable resistance memory device with a cell-over-peripheral (COP) structure that includes row selection transistors, dummy row selection transistors, word lines, dummy word lines, bit lines, and dummy memory cells, where the number of row selection transistors equals the number of word lines, and the number of dummy row selection transistors is fewer than dummy word lines, with ends of dummy word lines merged to reduce the overall number of transistors and wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dummy word lines are connected to separate dummy row selection transistors, then each dummy word line can be independently controlled, but the number of transistors and wiring complexity increases
Solution Approach 1:
Multiple dummy word lines are merged and connected to a single shared dummy row selection transistor through a dummy word line connection node. This reduces the total number of dummy row selection transistors from potentially many (one per dummy word line) to just one, thereby reducing device complexity and transistor count while still allowing collective control of all dummy word lines for maintaining memory cell operations
2Reliability
If the number of dummy row selection transistors equals the number of dummy word lines, then each dummy word line has dedicated control, but chip size and manufacturing cost increase
Solution Approach 1:
A single dummy row selection transistor serves multiple dummy word lines simultaneously by connecting them through a shared connection node. This multi-functional approach allows one transistor to perform the control function that would otherwise require multiple transistors, reducing chip area while maintaining the reliability needed for proper memory cell operations during read/write processes
Data Source
AI summary
An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.