Variable Resistance Memory Cells with Multi-Level Data Storage Regions
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Solution Overview
Problem
Reducing cell pitch and area to achieve high integration in variable resistance memory apparatuses is challenging, leading to degraded electrical characteristics and reliability due to voids in data storage units, necessitating the implementation of a multi-level cell for high integration and large capacity.
Innovation Solution
A variable resistance memory apparatus with a multi-level cell design, featuring memory cells with multiple data storage regions of varying widths and heights, and a manufacturing method involving the formation of switching devices, electrodes, and data storage units on a semiconductor substrate, allowing for different program volumes under the same current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell pitch and area are reduced to achieve high integration, then integration density is improved, but electrical characteristics and reliability are degraded due to voids in data storage units
Solution Approach 1:
The patent transitions from a single data storage unit per cell to multiple data storage units arranged in different dimensions (stacked vertically and/or horizontally). This multi-dimensional arrangement increases storage capacity without proportionally reducing cell pitch, thereby maintaining manufacturing precision and avoiding void formation while achieving high integration density.
Solution Approach 2:
The patent divides a single large data storage unit into multiple smaller data storage units within one memory cell. This segmentation allows for better distribution of material, reduced stress concentration, and improved manufacturing control, preventing void formation while maintaining high integration capacity.
2Quantity of substance
If cell pitch is reduced to implement multi-level cell, then storage capacity is improved, but manufacturing precision is degraded due to void formation
Solution Approach 1:
The patent implements a nested structure where multiple data storage units are stacked vertically within the same planar footprint, or arranged in a hierarchical configuration. This nesting approach increases storage capacity without requiring proportional reduction in cell pitch, thereby maintaining manufacturing precision and avoiding void formation during fabrication.
3Adaptability or versatility
If data storage units are formed with different dimensions, then multi-level cell functionality is achieved, but device complexity is increased
Solution Approach 1:
The patent applies local quality by creating data storage units with different dimensions (width, length, or height) at specific locations within the memory cell array. This allows different storage capacities to be assigned to different regions, achieving multi-level cell functionality while maintaining a relatively simple overall structure through localized variations rather than global complexity.
Data Source
AI summary
A variable resistance memory apparatus and a method of manufacturing the same are provided. The variable resistance memory apparatus includes a plurality of memory cells. Each of the memory cells includes a plurality of data storage regions. The plurality of data storage regions have different widths from each other.