3D Stacked Variable Resistance Memory Device With Conductive Pillar
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density and operational reliability while maintaining low power consumption and high performance.
Innovation Solution
A semiconductor memory device is designed with a stacked structure of insulating layers and variable resistance layers, including a conductive pillar and second variable resistance layer surrounding its sidewall, along with conductive lines and slit insulating layers, to enhance integration density and operational reliability. The device uses chalcogenide materials like GeSe for variable resistance, allowing for both memory and select device functions, and employs specific manufacturing processes to compensate for element loss during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory device structures are used, then manufacturing processes are simpler, but integration density and operational reliability cannot be increased
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures with variable resistance layers arranged vertically. Multiple insulating layers and variable resistance layers are stacked in the thickness direction, creating a vertical architecture that increases integration density while maintaining manufacturability through standardized layer formation processes.
Solution Approach 2:
The patent implements nested structures where conductive pillars are surrounded by second variable resistance layers, which are in turn surrounded by first variable resistance layers. This nested arrangement allows multiple functional layers to occupy the same footprint area, increasing storage capacity without proportionally increasing device complexity.
2Manufacturing precision
If element loss during etching is not compensated, then manufacturing process is simpler, but memory hole formation precision deteriorates
Solution Approach 1:
The patent applies a protective coating to the variable resistance layer before etching processes. This preliminary protective action prevents element loss during subsequent etching steps, ensuring precise memory hole formation without requiring complex in-situ compensation mechanisms during the etching process itself.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between variable resistance layers. These intermediary layers serve as etch stop layers that prevent excessive etching and element loss, maintaining manufacturing precision while using simple, well-established deposition and etching processes.
3Quantity of substance
If integration density is increased through stacking, then storage capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating units of insulating layers and variable resistance layers. Each unit can be formed using similar manufacturing processes, allowing incremental increases in integration density by simply adding more repeating units rather than redesigning the entire structure.
Solution Approach 2:
The patent designs the stacked structure so that each layer serves multiple functions: insulating layers provide both electrical isolation and structural support, while variable resistance layers provide both storage functionality and etch stop functions. This multi-functionality reduces the need for additional specialized layers, keeping manufacturing complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases integration density and operational reliability of semiconductor memory devices by enabling efficient data storage and retrieval through varying threshold voltages based on pulse polarity, while maintaining low power consumption and simplifying manufacturing processes.
Implementation Method 1
a first variable resistance layer which is in contact with the conductive pillar and surrounds a part of the conductive pillar in a radial direction
Implementation Method 2
The device uses chalcogenide materials like GeSe for variable resistance
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.