Variable Resistance Memory Cell Potential Control

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Solution Overview

Problem

Existing variable-resistance memory devices require intricate potential control mechanisms for word and bit lines, involving multiple signal inputs and complex biasing conditions, which complicates the control of potentials and can lead to inefficiencies and errors in operations.

Innovation Solution

A semiconductor memory device design that incorporates a pair of variable-resistance elements and diodes connected in series between nodes connected to row and column select lines, with dedicated control circuits for each line, allowing for simplified potential control using shared or split select lines in vertically stacked memory cell arrays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two potential adjusting mechanisms are used for word lines and bit lines, then selectivity is enhanced, but device complexity increases

Engineering Contradiction:
ImproveselectivityVSAvoidpotential control mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the potential adjusting function from both word lines and bit lines, concentrating it solely on the bit lines. By removing the potential adjusting mechanism from word lines and retaining it only on bit lines, the invention reduces device complexity while preserving selectivity through the diode's inherent directional conduction properties.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If two potential adjusting mechanisms are used for word lines and bit lines, then selectivity is enhanced, but ease of operation deteriorates

Engineering Contradiction:
ImproveselectivityVSAvoidpotential control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent simplifies ease of operation by extracting the potential adjusting requirement from word lines. Since word lines no longer need potential adjustment, their control becomes trivial, and the overall potential control operation is eased while selectivity is maintained through bit line adjustment and diode characteristics.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If intricate potential control is implemented, then selectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
ImproveselectivityVSAvoidpotential control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent reduces manufacturing precision requirements by extracting the potential control function from word lines. This eliminates the need for precise potential control circuitry in word line drivers, simplifying the manufacturing process while maintaining selectivity through bit line control and diode properties.

Inventive Principle:
Principle #2Taking out (Extraction)

4Reliability

If multiple signal inputs are involved in potential control, then selectivity is enhanced, but device complexity increases

Engineering Contradiction:
ImproveselectivityVSAvoidsignal control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces signal control complexity by extracting the potential adjustment requirement from word lines. This eliminates the need for complex signal coordination between word line and bit line potential adjusters, simplifying the overall signal control architecture while preserving selectivity through bit line control and diode rectification.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7535748B2Semiconductor memory device
Publication Date: 2009.05.19 PANASONIC SEMICON SOLUTIONS CO LTD
  • US7535748B2 patent drawing
  • US7535748B2 patent drawing
  • US7535748B2 patent drawing

AI summary

A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.