Variable Resistance Memory Driving Method Using Asymmetric Pulse Widths

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Solution Overview

Problem

Variable resistance nonvolatile memory elements face issues with endurance characteristics, as the reliability of resistance value changes decreases with repeated writes, leading to potential write errors.

Innovation Solution

A method for driving a nonvolatile memory element involving a variable resistance layer and a field-effect transistor, where the resistance state is changed using specific voltage pulses, with the writing pulse having a shorter width than the erasing pulse, and the polarity and pulse widths are optimized to maintain reliable resistance changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage pulses are applied to change the resistance state of the variable resistance layer, then the memory operation is performed, but repeated writes cause unreliable resistance value changes and write errors

Engineering Contradiction:
Improveendurance characteristicsVSAvoidwrite operation reliability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different pulse widths to writing and erasing voltage pulses. Specifically, the writing voltage pulse has a shorter pulse width than the erasing voltage pulse. This parameter differentiation optimizes the resistance change process, ensuring reliable state transitions and improving endurance characteristics by preventing cumulative damage from repeated operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent dynamically adjusts the pulse width parameters based on the operation type (writing or erasing). By making the pulse width dependent on the specific operation requirements rather than using a fixed duration, the system achieves more reliable resistance state changes and reduces write errors through optimized temporal control of voltage application.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the pulse width of writing voltage pulse is made shorter than erasing voltage pulse, then endurance characteristics are improved, but the control complexity increases

Engineering Contradiction:
Improveendurance characteristicsVSAvoidcontrol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent establishes a specific parameter relationship where the pulse width of the writing voltage pulse is shorter than that of the erasing voltage pulse. This parameter change simplifies the control logic by providing a clear design rule rather than requiring complex real-time adjustments, thereby improving endurance without significantly increasing control complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the endurance characteristics of the nonvolatile memory element, ensuring reliable memory operations and improved resistance state stability even after multiple write cycles.

Implementation Method 1

a variable resistance layer which is provided between the first terminal and the second terminal and has a resistance value that reversibly changes according to a voltage pulse applied to between the first terminal and the second terminal

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Data Source

PatentUS9153319B2Method for driving nonvolatile memory element, and nonvolatile memory device having a variable resistance element
Publication Date: 2015.10.06 PANASONIC SEMICON SOLUTIONS CO LTD
  • US9153319B2 patent drawing
  • US9153319B2 patent drawing
  • US9153319B2 patent drawing

AI summary

A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.