Variable Resistance Memory Read Circuit Using Mirror Currents
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Solution Overview
Problem
Conventional read circuits for phase-change memory devices face instability due to varying threshold voltages and require high-step-up voltages, leading to low current efficiency and large area occupation.
Innovation Solution
A read circuit comprising a comparison circuit, a read current control circuit with a PMOS transistor, a mirror circuit, and a sense circuit, which provides a controlled read current and mirror current to stabilize voltage clamping and eliminate the need for a step-up voltage pumping circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clamping element using NMOS transistor is used to maintain voltage, then voltage clamping function is achieved, but the clamping operation becomes unstable due to threshold voltage variation with process and temperature
Solution Approach 1:
The patent changes the transistor type from NMOS to PMOS for the clamping element. PMOS transistors exhibit more stable threshold voltage characteristics across process variations and temperature ranges compared to NMOS transistors, thereby improving clamping operation stability without requiring complex compensation circuits
Solution Approach 2:
The patent introduces a mirror circuit that copies the gate voltage of the PMOS clamping transistor to generate a corresponding mirror current. This mirroring mechanism ensures that the clamping voltage remains stable and consistent, compensating for any variations through the replicated voltage reference
2Power
If a high-level step-up voltage Vpp generated by pumping circuit is used to generate read current, then sufficient read current is achieved, but current efficiency decreases and chip area increases
Solution Approach 1:
The patent extracts and eliminates the unnecessary step-up voltage pumping circuit from the read current generation path. By using the available power supply voltage directly with a PMOS transistor configured as a current source, the circuit achieves sufficient read current without the energy loss and area overhead of voltage pumping
Solution Approach 2:
The PMOS transistor in the read current control circuit operates in saturation region to self-regulate the read current based on the gate voltage from the mirror circuit. This self-service mechanism eliminates the need for external step-up voltage generation, improving current efficiency while maintaining adequate read current levels
3Power
If a high-level step-up voltage Vpp generated by pumping circuit is used to generate read current, then sufficient read current is achieved, but chip area occupation increases
Solution Approach 1:
The patent removes the bulky step-up voltage pumping circuit from the design. The read current is generated using a simple PMOS transistor and mirror circuit configuration that occupies minimal chip area while still providing sufficient current magnitude for reliable memory cell reading
Solution Approach 2:
The patent merges the voltage clamping function and read current generation function into a unified PMOS transistor-based circuit. The same PMOS transistor that clamps the voltage also serves as the current source when operated in saturation, eliminating the need for separate pumping circuitry and reducing overall chip area
Data Source
AI summary
A nonvolatile memory device includes a variable resistance memory element and a read circuit coupled to the variable resistance memory element at a first signal node and configured to provide a read current to the variable resistance memory element via the first signal node, to a provide a mirror current at a second signal node responsive to the cell current and to generate an output signal indicative of a state of the variable resistance memory element responsive to a voltage at the second signal node.