Variable Resistance Memory Read Pulse Polarity Control
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Solution Overview
Problem
Variable resistance memory devices face read disturbance issues due to excessive current application during data retrieval, causing unintended phase transitions in the memory cell, which affects operational reliability.
Innovation Solution
The solution involves controlling the read pulse polarity based on the greater amorphization start current values determined by pulses of opposite polarities, ensuring that the read operation is performed under conditions that minimize phase transitions, thereby reducing read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a read pulse is applied to retrieve data from the variable resistance memory cell, then data can be read, but excessive current causes unintended phase transitions leading to read disturbance
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the polarity of the read pulse based on the stored data state. When data '0' is stored, a positive read pulse is applied; when data '1' is stored, a negative read pulse is applied. This parameter change in pulse polarity ensures that the read current never exceeds the amorphization start current, preventing unintended phase transitions while still enabling accurate data retrieval.
Solution Approach 2:
The patent uses inversion by applying opposite polarities of read pulses depending on the stored data state. Instead of using a unidirectional read pulse that might cause disturbance, the system inverts the pulse polarity based on the data state, ensuring that the current direction and magnitude are always appropriate for reading without causing phase transitions.
2Productivity
If a write pulse with high current is applied to change the resistance state, then data can be written, but it may cause unintended phase transitions during subsequent read operations
Solution Approach 1:
The patent applies preliminary action by determining and storing the amorphization start current value during the write operation or initialization phase. This pre-determined threshold value is then used to control the polarity and magnitude of subsequent read pulses, ensuring that read operations never exceed the safe current threshold that would cause unintended phase transitions, thereby maintaining data integrity.
Solution Approach 2:
The system uses feedback by comparing the stored data state with the amorphization start current threshold to dynamically select the appropriate read pulse polarity. The control logic receives feedback about the stored state and adjusts the read pulse parameters accordingly, ensuring that the read operation remains within safe current limits and prevents unintended phase transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the operational reliability of variable resistance memory devices by suppressing phase transition phenomena during read operations, maintaining the set state of the memory cell and enhancing data integrity.
Implementation Method 1
A variable resistance memory device has been proposed as an example of a next generation memory device. The variable resistance memory device may have one of different resistance states depending on a voltage or a current applied to a memory cell
Implementation Method 2
The peripheral circuit may control the read pulse to have a polarity corresponding to a greater value of first and second amorphization start current values of the variable resistance memory cell
Data Source
AI summary
The present technology provides an electronic device, a memory device, and a method of operating a memory device. The memory device includes a memory cell array including a variable resistance memory cell coupled to a first conductive line and a second conductive line, and a peripheral circuit configured to provide a write pulse or a read pulse to the variable resistance memory cell through the first conductive line. The write pulse is controlled to have one of a first polarity and a second polarity that are opposite to each other. The read pulse is controlled to have a polarity corresponding to a greater value of first and second amorphization start current values of the variable resistance memory cell, the first amorphization start current value being determined by a first pulse having the first polarity, the second amorphization start current value being determined by a second pulse having the second polarity.