Variable Resistance Memory Cell Architecture for Scalable Non-Volatile Storage
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in achieving low power consumption, high speed, high density, and scalability below 65 nanometers, with existing resistance switching memories being speculative and lacking practical implementation.
Innovation Solution
The development of novel memory architectures using variable resistance materials, including chalcogenides and correlated electron materials, integrated with diodes and field effect transistors, allowing for resistance-based and capacitance-based reading and writing without electron tunneling through insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Flash memory is used to achieve high density and non-volatility, then storage capacity is improved, but scalability below 65 nanometers is limited and power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameter from charge storage (Flash) to resistance state storage (RRAM). By utilizing variable resistance materials that can be switched between high and low resistance states through voltage application, the invention achieves scalability to smaller dimensions without the physical limitations of charge trapping mechanisms used in Flash memory.
2Duration of action of stationary object
If EEPROM technology is used to achieve non-volatility and read/write capability, then data retention is improved, but write/erase cycle lifetime is limited to 10^5-10^6 cycles
Solution Approach 1:
The patent replaces the mechanical/electrical wear mechanism of charge tunneling through insulating layers (in EEPROM) with a purely electrical resistance switching mechanism in RRAM. The variable resistance material undergoes reversible resistance changes without physical degradation, enabling endurance exceeding 10^12 cycles while maintaining non-volatile data retention.
3Duration of action of stationary object
If phase change memory materials are used to achieve resistance switching, then non-volatility is improved, but manufacturing complexity increases due to speculative and unproven fabrication processes
Solution Approach 1:
The patent changes the material state transition mechanism from phase change (amorphous/crystalline) to resistance state change in correlated electron materials. This approach uses standard semiconductor fabrication techniques to deposit thin films of materials like nickel oxide, avoiding the complex heating and cooling cycles required for phase change memory while achieving comparable non-volatile performance.
4Duration of action of stationary object
If quantum tunneling mechanisms are used in EEPROM to write data, then non-volatile storage is achieved, but power consumption increases due to high voltage requirements (12-21 volts)
Solution Approach 1:
The patent changes the write mechanism from quantum tunneling requiring high voltages (12-21V) to resistive switching achievable at low voltages (1-5V). The variable resistance material directly transitions between resistance states through voltage-induced changes in electron correlation, eliminating the need for high-voltage tunneling barriers and significantly reducing power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These architectures enable denser memory arrays with faster program and erase cycles, maintaining non-volatility and scalability to smaller sizes while reducing power consumption and increasing endurance.
Implementation Method 1
a variable resistance material (VRM) formed over a semiconductor channel
Data Source
AI summary
An integrated circuit memory cell including: a semiconductor having a first active area, a second active area, and a channel between the active areas; and a layer of a variable resistance material (VRM) directly above the channel. In one embodiment, there is a first conductive layer between the VRM and the channel and a second conductive layer directly above the VRM layer. The VRM preferably is a correlated electron material (CEM). The memory cell comprises a FET, such as a JFET or a MESFET. In another embodiment, there is a layer of an insulating material between the VRM and the channel. In this case, the memory cell may include a MOSFET structure.