Variable Resistance Memory Device With Shared Bit Line And SOT Layers
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Solution Overview
Problem
Current variable resistance memory devices face challenges in achieving high integration density and efficient memory cell operations due to limitations in electrical and physical connection relationships between components.
Innovation Solution
The proposed variable resistance memory device incorporates a matrix arrangement of memory cells with spin-orbit torque (SOT) layers and variable resistance layers, utilizing shared bit lines and optimized wiring structures to enhance integration density and improve write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are highly integrated to increase density, then integration density improves, but electrical connection complexity and operational efficiency deteriorate
Solution Approach 1:
The patent merges the bit line and common source line functions into a single shared electrical path. The bit line serves dual purposes: as a bit line for selected memory cells and as a common source line for adjacent memory cells, reducing the total number of separate conductors needed and simplifying the electrical connection architecture while maintaining high integration density
Solution Approach 2:
The bit line is designed with multi-functionality to operate as both a bit line and a common source line depending on the selected memory cell region. This universal design allows the same physical conductor to serve multiple functional roles, reducing connection complexity without sacrificing integration density
2Device complexity
If shared bit lines are used to reduce wiring complexity, then device complexity decreases, but read disturbance to adjacent cells increases
Solution Approach 1:
The patent segments the memory cell array into distinct regions with different bit line connections. Memory cells in different rows are connected to different bit lines, allowing selective activation. When reading from one row, only the corresponding bit line is activated, preventing read disturbance to adjacent rows while still utilizing shared source line functionality
Solution Approach 2:
The patent implements local quality by providing different connection configurations for different regions of the memory array. Each memory cell region has its own bit line connection while sharing common source line infrastructure, allowing localized control that prevents read disturbance to distant cells while maintaining overall wiring simplicity
3Area of stationary object
If compact memory cell layout is implemented to increase integration density, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric layout design where memory cells in different rows have different connection configurations. This asymmetry allows for optimized spacing and routing that reduces sensitivity to alignment variations during manufacturing, enabling compact cell layouts without proportionally increasing precision requirements
Solution Approach 2:
The patent resolves layout constraints by utilizing three-dimensional layering and vertical stacking of conductors. By moving connections to different vertical layers and using through-substrate vias, the design achieves compact planar footprint while reducing the impact of lateral alignment errors, as precision is shifted to the vertical dimension where control is more precise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed switching, low read disturbance, and increased integration density, enabling efficient data storage and retrieval in a compact electronic memory system.
Implementation Method 1
a plurality of spin-orbit torque (SOT) layers on the plurality of variable resistance layers
Data Source
AI summary
A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.