Variable Resistance Memory Silicide Interface Fabrication
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved variable resistance characteristics, which are essential for advanced memory applications, particularly in miniaturized, low-power, high-performance electronic devices.
Innovation Solution
The method involves forming a semiconductor memory device by creating a crystalized doped layer over a substrate, followed by a barrier layer and a metal layer, with the barrier layer reacting with the metal layer to form a silicide layer, and incorporating a variable resistance element such as a transitional metal oxide or phase-changing material, to enhance resistance switching properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional doping methods are used to form a doped layer, then the doping process is simple, but the variable resistance characteristics are insufficient for advanced memory applications
Solution Approach 1:
The patent applies parameter changes by transforming the crystalline doped layer into an amorphous state through ion implantation or laser annealing. This phase transition modifies the electrical properties of the doped layer, enabling improved variable resistance characteristics necessary for advanced memory applications while maintaining a relatively simple fabrication sequence.
Solution Approach 2:
The patent creates a composite structure by forming a silicide layer through the reaction between the amorphous doped layer and a metal layer. This composite material combination (amorphous silicon + metal) provides superior variable resistance properties compared to conventional doped layers, addressing the reliability requirement while the integrated fabrication process keeps complexity manageable.
2Reliability
If a barrier layer is formed between the doped layer and metal layer, then interface resistance is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The patent uses the amorphous doped layer itself as an intermediary barrier between the substrate and the metal layer. Through controlled ion implantation or laser annealing, this layer develops barrier properties that reduce interface resistance without requiring a separate barrier material layer, thus maintaining fabrication efficiency while achieving the desired electrical interface characteristics.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the doped layer by transforming it from crystalline to amorphous state. This parameter change creates a natural barrier effect at the interface with the metal layer, reducing interface resistance without adding extra fabrication steps for a separate barrier layer.
3Reliability
If the doped layer is transformed into an amorphous state, then variable resistance characteristics are improved, but additional processing steps are required
Solution Approach 1:
The patent exploits phase transitions by transforming the doped layer from a crystalline state to an amorphous state through ion implantation or laser annealing. This phase transition is the key mechanism that enables superior variable resistance characteristics and resistance switching properties, which are essential for advanced memory applications. The process integrates this phase transition into existing fabrication workflows.
Solution Approach 2:
The patent performs the amorphization of the doped layer as a preliminary action before forming the metal layer and silicide structure. By preparing the doped layer in the amorphous state in advance, subsequent processing steps can proceed efficiently, and the desired resistance switching properties are established before final device assembly, reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance and characteristics of variable resistance elements, enabling efficient data storage and processing in electronic devices, particularly in microprocessors, processors, and memory systems, by reducing interface resistance and enhancing switching properties.
Implementation Method 1
The reacting of the barrier layer and the portion of the metal layer includes performing heat treatment on the barrier layer and the portion of the metal layer
Implementation Method 2
The reacting of the barrier layer with the portion of the metal layer including forming a silicide layer
Implementation Method 3
performing laser annealing to recrystallize the doped region to form the crystalized doped layer
Implementation Method 4
performing laser annealing to recrystallize the doped region to form the crystalized doped layer
Implementation Method 5
The forming of the barrier layer includes performing ion implantation into the crystalized doped layer
Data Source
AI summary
An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.