Variable Resistance Memory Devices With Stacked Patterns
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high performance and low power consumption, particularly in providing variable resistance patterns with different switching characteristics and resistance levels, which are essential for next-generation memory applications.
Innovation Solution
A variable resistance memory device is designed with multiple variable resistance patterns of varying shapes, thicknesses, and materials, stacked vertically and connected in series, allowing for distinct resistance levels and switching characteristics by controlling the patterns with applied voltages, utilizing magnetic tunnel junctions and other materials for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple variable resistance patterns with different shapes, thicknesses, and materials are vertically stacked, then different resistance levels and switching characteristics are achieved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple variable resistance patterns (first, second, third patterns) with different geometries, thicknesses, and materials stacked vertically. Each pattern segment provides distinct resistance characteristics, allowing the system to achieve multiple resistance levels through series connection while maintaining manageable individual pattern complexity
Solution Approach 2:
The patent transitions from planar variable resistance patterns to vertically stacked three-dimensional structures. By adding the vertical dimension with different heights (first height, second height, third height) and stacking patterns at different levels, the device achieves diverse resistance characteristics without increasing lateral footprint, effectively managing complexity through spatial reorganization
2Adaptability or versatility
If variable resistance patterns are provided at different heights from the substrate, then different resistance levels are achieved, but manufacturing precision requirements increase
Solution Approach 1:
The variable resistance functionality is segmented into multiple discrete patterns positioned at different heights (first height, second height, third height) from the substrate. Each pattern can be independently fabricated with standard precision requirements, avoiding the need to manufacture a single complex structure with extremely tight tolerance requirements
Solution Approach 2:
The patent utilizes the vertical dimension (height from substrate) to differentiate resistance characteristics. By stacking patterns at progressively different heights rather than varying lateral dimensions, the manufacturing process can use standard lithography and deposition techniques with conventional precision requirements for each layer, cumulative precision being more achievable than single-step high-precision fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved memory performance by providing different resistance levels and switching characteristics, enabling efficient data storage and retrieval while maintaining low power consumption, suitable for both non-volatile and random access memory applications.
Implementation Method 1
Resistance of the MTJ pattern varies depending on magnetization directions of the magnetic layers. For example, the resistance of the MTJ pattern is greater when the magnetic layers have anti-parallel magnetization directions than when they have parallel magnetization directions.
Data Source
AI summary
A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.