Variable Resistance Memory Access Control via Selection Switches

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Solution Overview

Problem

Conventional nonvolatile memory devices with crosspoint structures face challenges in simplifying the control of successive accesses and achieving high integration due to increased layout area and capacitive coupling issues, leading to fluctuations in read speed and power consumption.

Innovation Solution

A variable resistance nonvolatile memory device with a substrate having bit lines and word lines in multiple layers, where memory cells are formed at crosspoints, and a control unit manages access using selection switch elements and via groups to maintain consistent voltage application across layers, eliminating the need for changing potentials in each cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional crosspoint structure is used, then memory cells can be formed at crosspoints of bit lines and word lines, but control of successive accesses becomes complex and layout area increases

Engineering Contradiction:
Improvememory cell formationVSAvoidaccess control
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The bit lines are divided into multiple groups (first bit line group and second bit line group) that are selectively connected to global bit lines through selection switch elements. This segmentation allows independent control of different bit line groups, simplifying the access control mechanism while maintaining the crosspoint structure's manufacturing simplicity.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional crosspoint structure is used, then memory cells can be formed at crosspoints, but layout area increases due to complex voltage control requirements

Engineering Contradiction:
Improvememory cell formationVSAvoidlayout area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The selection switch elements serve multiple functions: they control the connection between bit line groups and global bit lines, manage voltage distribution, and enable simplified access control sequences. This multi-functionality eliminates the need for separate control circuits and reduces the overall layout area while preserving the crosspoint structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If successive accesses are made to memory cells, then data can be read sequentially, but read speed fluctuates due to capacitive coupling

Engineering Contradiction:
Improvesequential accessVSAvoidread speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The selection switch elements dynamically connect or disconnect bit line groups to global bit lines based on the access sequence. This dynamic control allows the system to maintain consistent voltage relationships during successive accesses, preventing read speed fluctuations caused by capacitive coupling while enabling efficient sequential data reading.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration simplifies access control, reduces power consumption, and maintains consistent read speed regardless of memory cell position, enhancing integration and operational efficiency.

Implementation Method 1

a variable resistance element, a resistance state of which reversibly changes based on an electrical signal

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Data Source

PatentUS8848424B2Variable resistance nonvolatile memory device, and accessing method for variable resistance nonvolatile memory device
Publication Date: 2014.09.30 PANASONIC SEMICON SOLUTIONS CO LTD
  • US8848424B2 patent drawing
  • US8848424B2 patent drawing
  • US8848424B2 patent drawing

AI summary

A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.