Variable Resistance Memory Device Trench Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Next-generation semiconductor memory devices require improved resistance variability and reduced power consumption, while maintaining electric characteristics and preventing interference between memory cells.
Innovation Solution
A variable resistance memory device is designed with a substrate, bottom electrodes, a first interlayer insulating layer with trenches exposing the electrodes, and variable resistance patterns aligned with top electrodes, along with a diffusion preventing pattern and heat loss preventing layer to enhance isolation and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If variable resistance patterns are provided in a trench to improve resistance variability control, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The memory device structure is segmented into distinct functional components: bottom electrodes, variable resistance patterns confined within trenches, interlayer insulating layers, and top electrodes. This segmentation isolates the variable resistance patterns spatially, enabling precise control of resistance variability while maintaining a manageable overall device architecture through modular organization.
Solution Approach 2:
The variable resistance patterns are positioned within trenches that extend in a first direction, while top electrodes extend in a second direction crossing the first direction. This orthogonal arrangement in multiple dimensions allows precise control of resistance characteristics through geometric configuration without requiring excessive structural complexity in a single plane.
2Reliability
If diffusion preventing patterns are added between variable resistance patterns and top electrodes to prevent interference, then reliability is improved, but device complexity increases
Solution Approach 1:
A diffusion preventing pattern is introduced as an intermediary layer between the variable resistance patterns and the top electrode. This intermediate structure prevents unwanted diffusion or interference between the two components, thereby improving device reliability and stability without requiring fundamental changes to the overall device architecture.
Solution Approach 2:
The diffusion preventing pattern is applied locally at the interface between variable resistance patterns and top electrodes, rather than throughout the entire device. This localized approach provides targeted interference prevention exactly where needed, improving reliability without adding unnecessary complexity to other parts of the device.
3Use of energy by moving object
If heat loss preventing layers are introduced to reduce power consumption, then energy efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
Heat loss preventing layers are introduced to modify the thermal parameters of the device, reducing heat dissipation from the variable resistance patterns. By changing the thermal conductivity or heat retention properties through these layers, power consumption is reduced while the manufacturing process remains compatible with existing semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves electric characteristics and reduces power consumption by allowing precise control of resistance states and preventing interference between memory cells, thus enhancing the reliability and efficiency of the memory device.
Implementation Method 1
Material constituting the next generation semiconductor memory devices may have a different resistance depending on a current forced thereto or a voltage applied thereto
Implementation Method 2
a diffusion preventing pattern between the variable resistance patterns and the top electrode
Data Source
AI summary
Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.


