Variable Resistance Memory Cell Structure for Data Retention

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Solution Overview

Problem

Current semiconductor memory devices, particularly volatile and nonvolatile memory devices, face limitations in reliability and operational characteristics, such as data loss in power cutoffs and restricted program/erase cycles, which affect their performance and durability.

Innovation Solution

The development of a variable resistance memory system that includes a memory array with variable resistance memory cells, each comprising a well and a cell structure with a variable resistance layer, along with a switch device to control current flow, enabling improved data retention and operational efficiency through advanced voltage and current management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional volatile memory devices are used, then fast read/write operations are achieved, but data is lost when power supply is cut off

Engineering Contradiction:
Improveread/write operation speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The memory system is segmented into volatile memory devices for fast read/write operations and variable resistance memory devices for reliable data retention. This segmentation allows each component to perform its optimal function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The variable resistance memory device acts as an intermediary backup system that receives copies of important data from the volatile memory, ensuring data persistence without affecting the speed of the primary volatile memory operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional nonvolatile memory devices are used, then data retention is maintained, but program/erase cycle endurance is restricted

Engineering Contradiction:
Improvedata retentionVSAvoidprogram/erase cycle endurance
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The variable resistance memory device utilizes materials and mechanisms that enable extensive program/erase cycle endurance beyond conventional nonvolatile memory limitations, achieving over 10^18 cycles while maintaining data retention capabilities.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If variable resistance memory cells with switch devices are used, then current flow is controlled for improved operational characteristics, but device complexity increases

Engineering Contradiction:
Improveoperational characteristicsVSAvoidcell structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The switch device in the variable resistance memory cell serves multiple functions: controlling current flow during programming, enabling read operations, and protecting the variable resistance layer from excessive current. This multi-functionality justifies the added complexity by delivering superior operational characteristics.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the reliability and operational characteristics of memory devices by allowing for improved data retention, reduced power consumption during programming, and increased endurance of program/erase cycles, leading to faster read/write operations and improved storage capabilities.

Implementation Method 1

a variable resistance layer on the structure

Methodology Applied
Scientific EffectVariable resistance: Electrical Resistance

Data Source

PatentUS8379441B2Variable resistance memory and memory system including the same
Publication Date: 2013.02.19 SAMSUNG ELECTRONICS CO LTD
  • US8379441B2 patent drawing
  • US8379441B2 patent drawing
  • US8379441B2 patent drawing

AI summary

A variable resistance memory array includes at least one variable resistance memory cell, wherein each variable resistance memory cell includes a well having a first type; and a cell structure on the well, the cell structure including a structure having a second type different from the first type and a variable resistance layer on the structure.