Variable Resistance Memory Word Line Resistance Compensation
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Solution Overview
Problem
Variable resistance memory devices face challenges in maintaining uniform current levels across memory cells due to differences in word line parasitic resistance, which affects read margin and reliability, and can lead to incorrect data storage or reduced endurance.
Innovation Solution
Incorporating bit line select circuits with transistors of varying resistances, such as different channel lengths or widths, to compensate for word line resistance differences between memory cells and the address decoder, ensuring uniform current distribution across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are connected to the address decoder through word lines of different lengths, then the memory device can accommodate more memory cells, but the word line parasitic resistance varies causing non-uniform current levels
Solution Approach 1:
The patent applies local quality by configuring bit line select transistors with different resistance values at different locations in the memory array. Specifically, transistors connected to memory cells farther from the address decoder have lower resistance values to compensate for the higher word line parasitic resistance in those regions, while transistors closer to the decoder have higher resistance values. This spatial variation in transistor resistance compensates for the spatial variation in word line resistance, maintaining uniform current levels across all memory cells.
2Reliability
If transistors with different resistances are used to compensate for word line resistance, then current uniformity improves, but device complexity increases
Solution Approach 1:
The patent implements parameter changes by systematically varying the resistance values of bit line select transistors based on their position in the memory array. The resistance values are adjusted in a graded manner corresponding to the distance from the address decoder, creating a compensation profile that counteracts the word line resistance gradient. This controlled parameter variation achieves current uniformity while maintaining a systematic and manufacturable design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution maintains uniform current levels across memory cells, enhancing read margin and reliability, preventing incorrect data storage and improving memory cell endurance by compensating for word line parasitic resistance variations.
Implementation Method 1
the first and second transistors have different resistances that compensate for the difference in word line resistance
Data Source
AI summary
Memory devices include a row decoder, a first variable resistance memory cell connected to a first bit line and connected to the row decoder by a word line and a second variable resistance memory cell connected to a second bit line and connected to the row decoder by the word line. The memory devices further include a bit line select circuit coupled to the first and second bit lines and configured to compensate for a difference in word line resistance between the row decoder and the respective first and second memory cells. In some embodiments, the bit line select circuit includes first and second transistors configured to selective respective ones of the first and second bit lines and the first and second transistors have different resistances that compensate for the difference in word line resistance.