Variable Resistance Memory Word Line Thickness Optimization

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Solution Overview

Problem

Current variable resistance memory devices face challenges in improving electrical characteristics due to the snap back phenomenon, which affects data retention and read/write operations, primarily influenced by the capacitance between word lines.

Innovation Solution

The design includes memory cell stacks with word lines of varying thicknesses, allowing for controlled snap back phenomenon by adjusting the thickness of the word lines, thereby enhancing the electrical characteristics of the variable resistance memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the thickness of word lines is increased to reduce read disturbance, then data retention improves, but the snap back phenomenon becomes more severe affecting write operations

Engineering Contradiction:
Improvedata retentionVSAvoidsnap back phenomenon
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different word line thicknesses to different memory cell stacks. Specifically, first memory cell stacks have word lines with a first thickness, while second memory cell stacks have word lines with a second thickness different from the first. This local differentiation allows each stack type to be optimized for specific functions: thicker word lines for reduced read disturbance in data retention, and thinner word lines for mitigated snap back phenomenon in write operations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The memory device is segmented into multiple memory cell stacks with different word line thicknesses. The patent divides the memory array into first memory cell stacks and second memory cell stacks, where each stack type has uniformly different word line thicknesses. This segmentation enables independent optimization of electrical characteristics for different functional requirements within the same device.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If uniform word line thickness is used across all memory cell stacks, then manufacturing simplicity is maintained, but electrical characteristics cannot be optimized for different operational requirements

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidelectrical characteristics
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local quality by assigning different word line thicknesses to different memory cell stacks based on their functional requirements. First memory cell stacks use word lines with a first thickness optimized for their operations, while second memory cell stacks use word lines with a second thickness optimized for their operations. This approach maintains manufacturing feasibility through standardized processes while achieving optimized electrical characteristics for different operational modes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11100959B2Variable resistance memory device
Publication Date: 2021.08.24 SAMSUNG ELECTRONICS CO LTD
  • US11100959B2 patent drawing
  • US11100959B2 patent drawing
  • US11100959B2 patent drawing

AI summary

A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.