Variable Resistive Load for Nonvolatile Memory Read Stability
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Solution Overview
Problem
Nonvolatile memory devices employing P-channel transistors face instability and reduced operation range due to varying supply voltage levels, leading to erroneous read operations for both initial and programmed states.
Innovation Solution
Incorporating a variable resistive load portion between the bit line and supply voltage line, which adjusts resistance values based on the supply voltage level, and a bias generator to manage the operation of P-channel transistors, ensuring stable read margins across a wide range of voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed resistance load is used in P-channel nonvolatile memory devices, then the device structure is simple, but the read operation becomes unstable and operation range is limited due to varying supply voltage levels
Solution Approach 1:
The patent applies the dynamics principle by replacing the fixed resistance load with a variable resistive load portion whose resistance value dynamically changes according to the supply voltage level. When supply voltage is high, the resistance increases; when supply voltage is low, the resistance decreases. This dynamic adjustment compensates for voltage variations and maintains stable read operations across different supply voltage conditions, resolving the contradiction between structural simplicity and operational reliability.
Solution Approach 2:
The patent implements parameter changes by making the resistance value of the load portion variable rather than fixed. The resistance parameter is changed based on the supply voltage level to maintain appropriate voltage division ratios during read operations. This parameter adaptation allows the device to operate reliably across a wide range of supply voltages without requiring complex additional circuitry.
2Measurement precision
If supply voltage level is increased to improve read operation, then read margin improves, but operation range is reduced and erroneous reads occur for both initial and programmed states
Solution Approach 1:
The patent changes the resistance parameter of the load portion based on supply voltage level to maintain optimal read margins across different voltage conditions. By adjusting the resistance value dynamically, the system achieves both high read margin and wide operation range, eliminating the need to choose between the two.
Solution Approach 2:
The patent implements a feedback mechanism where the resistive load portion senses the supply voltage level and automatically adjusts its resistance value accordingly. This feedback control ensures that the voltage division ratio remains within optimal ranges for reliable read operations, maintaining both high measurement precision and wide adaptability to different supply voltage conditions.
Data Source
AI summary
A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.