Variable Resistive Memory Cell Forming with Dynamic Voltage Control
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Solution Overview
Problem
Conventional resistance change memory devices face challenges in achieving consistent resistance value variations among variable resistive elements, leading to difficulties in subsequent operations due to large variations in resistance values after set or forming operations.
Innovation Solution
A semiconductor memory device with a memory cell array and control circuit that applies a gradually changing voltage to selected lines, using a pulsing voltage to manage cell current and ensure compliance current is reached, thereby controlling resistance values effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a high voltage is applied to variable resistive elements during forming operation, then the resistance values become changeable between high and low states, but large variations in resistance values occur among multiple elements
Solution Approach 1:
The patent applies dynamic voltage control during forming operations. Instead of applying a static high voltage, the system dynamically adjusts voltage levels across multiple formation cycles. The voltage is raised in successive cycles (e.g., from 2.0V to 3.0V to 4.0V) to progressively modify the resistance states of variable resistive elements, thereby reducing initial large variations while maintaining formability.
Solution Approach 2:
The patent changes the voltage parameter across different formation cycles. By varying the voltage level applied during forming operations (using different voltage thresholds for first, second, and third formation cycles), the system optimizes the resistance state distribution among multiple elements, reducing variations while ensuring proper forming.
2Ease of manufacture
If conventional forming operations are used, then variable resistive elements can be formed, but subsequent operations become difficult due to large resistance variations
Solution Approach 1:
The system performs multiple formation cycles with dynamically increasing voltage levels. This dynamic approach ensures that variable resistive elements are properly formed while achieving more uniform resistance values, making subsequent read and write operations easier and more reliable.
Solution Approach 2:
The patent incorporates detection of resistance states during formation cycles and uses this feedback to adjust voltage levels. When resistance values are detected to be within desired ranges, the forming operation stops; otherwise, additional cycles with adjusted voltages are performed, ensuring optimal forming before subsequent operations.
3Device complexity
If simple voltage application is used during set operation, then the operation is simple, but resistance value variations remain large
Solution Approach 1:
The control circuit dynamically adjusts voltage levels during set operations across multiple cycles. The voltage is progressively increased (e.g., from 2.0V to 3.0V to 4.0V) to achieve uniform resistance state changes, reducing variations while maintaining reasonable control circuit complexity through automated voltage management.
Solution Approach 2:
The system changes voltage parameters across different set operation cycles to optimize resistance uniformity. By using different voltage thresholds and progressive voltage increases, the control circuit achieves better manufacturing precision without requiring overly complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and efficient set/reset operations, allowing for precise control of memory cells and reducing variations in resistance values, thereby improving the reliability and speed of memory cell operations.
Implementation Method 1
a control circuit which controls resistance values of variable resistive elements in such a way that a cell voltage is applied to a memory cell arranged at an intersection between a selected one of a plurality of first lines and a selected one of a plurality of second lines by applying a first voltage to the selected first line and by applying a second voltage to the selected second line
Implementation Method 2
The resistance change memory stores data therein by turning variable resistive elements into a low resistance state by a set operation and into a high resistance state by a reset operation
Data Source
AI summary
A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable resistive elements in a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected first line and a selected second line by applying first and second voltages to the selected first and second lines, respectively. The control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and a pulsing voltage as the second voltage to the selected second line.