Variable Resistive Memory Hierarchical Wordline Voltage Control
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Solution Overview
Problem
In variable resistive memory devices, the rising voltage of sub-wordlines during write and read operations can reduce the voltage difference between bitlines and sub-wordlines, leading to failed write and read operations due to insufficient current flow.
Innovation Solution
The implementation of a hierarchical wordline structure where only half or a quarter of memory blocks in each sector are activated during operations, using local bitline selecting signals to distribute memory cells across sub-wordlines, thereby maintaining stable sub-wordline voltages and reducing current flow to prevent voltage rises.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current flows from bitline to wordline during write operation, then write operation can be performed, but sub-wordline voltage rises reducing voltage difference and causing write failure
Solution Approach 1:
The memory array is divided into multiple memory blocks, each with its own local bitline selecting part. During write operations, only specific memory blocks are activated at a time, segmenting the current flow path. This prevents excessive current accumulation on sub-wordlines while still enabling write operations to targeted memory cells.
Solution Approach 2:
Instead of activating all memory blocks simultaneously during write operations, the invention activates only the necessary portion (half or quarter) of memory blocks. This partial activation reduces the total current flow through sub-wordlines, preventing voltage rise while maintaining write operation effectiveness in the activated blocks.
2Speed
If more memory blocks are activated during operations, then operational speed increases, but sub-wordline voltage rises causing read/write failures
Solution Approach 1:
The memory device is segmented into multiple sectors and blocks with hierarchical wordline structures. This segmentation allows parallel operation of multiple blocks while limiting current flow to each individual block's sub-wordlines, maintaining both speed and reliability.
Solution Approach 2:
The invention introduces a hierarchical wordline structure with main wordlines and sub-wordlines across multiple dimensions. This dimensional organization allows current to be distributed across different wordline levels, preventing excessive voltage rise on any single sub-wordline while enabling parallel operations.
3Use of energy by moving object
If voltage difference between bitline and sub-wordline is reduced, then power consumption decreases, but current flow becomes insufficient for successful operations
Solution Approach 1:
The invention dynamically controls wordline voltages based on operation type (read/write) and memory block activation status. By adjusting voltage parameters adaptively, the system maintains sufficient voltage difference for reliable operations while minimizing power consumption during idle or partially activated states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the undesirable rise in sub-wordline voltage, ensuring successful write and read operations by reducing current flow to sub-wordlines, thereby enhancing the operational reliability and efficiency of variable resistive memory devices.
Implementation Method 1
a variable resistive material or part 12 connected to the BL, a switching element 14 connected to the variable resistive part
Data Source
AI summary
A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of the memory cells in a second sector, local bitlines where each is in signal communication a memory cell, a local bitline selecting signal generator in signal communication with local bitline selecting signal paths, a first local bitline selecting signal path in signal communication with a first pair of the local bitlines, and a second local bitline selecting signal path in signal communication with a second pair of the plurality of local bitlines, where a first of the first pair of local bitlines is in signal communication with a first of the first pair of the memory cells in the first sector and a second of the first pair of local bitlines is in signal communication with a second of the second pair of the memory cells in the second sector, and a first of the second pair of local bitlines is in signal communication with a second of the first pair of the memory cells in the first sector and a second of the second pair of local bitlines is in signal communication with a first of the second pair of the memory cells in the second sector.