Variable Resistive Memory Power Mesh Segmentation
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Solution Overview
Problem
Current variable resistive memory devices face challenges in efficiently integrating two-terminal memory cells and optimizing power mesh structures to enhance resistance characteristics and capacitance performance.
Innovation Solution
The proposed solution involves a semiconductor substrate with a device layer and upper metal interconnects forming a power mesh structure, where alternating first and second uppermost metal interconnects receive different voltages, creating a reservoir capacitor between them, and memory cells are arranged between these interconnects, utilizing chalcogenide materials for variable resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional power mesh structure is used in variable resistive memory devices, then the basic interconnect function is provided, but the interconnect resistance characteristics are insufficient and capacitance performance is not optimized
Solution Approach 1:
The uppermost metal interconnect is divided into multiple interconnect lines (first, second, third, fourth uppermost metal interconnects) with alternating voltage assignments. This segmentation creates multiple reservoir capacitors distributed across the memory cell array, improving interconnect resistance characteristics without requiring a completely new power mesh architecture.
Solution Approach 2:
The uppermost metal interconnect serves dual functions: it provides power distribution to memory cells through the alternating voltage pattern and simultaneously forms reservoir capacitors with underlying interconnects. This multi-functionality reduces the need for separate capacitor structures, optimizing capacitance performance while maintaining power mesh functionality.
2Reliability
If alternating voltage interconnects are implemented to create reservoir capacitors, then capacitance performance is enhanced, but the device structure becomes more complex
Solution Approach 1:
The power distribution function and capacitance storage function are merged into the same uppermost metal interconnect layer. By alternating voltage assignments across adjacent interconnect lines, the structure simultaneously provides power to memory cells and forms reservoir capacitors, eliminating the need for separate capacitor regions and reducing overall device complexity.
Solution Approach 2:
The invention utilizes the vertical stacking dimension to create reservoir capacitors by forming capacitive coupling between the uppermost metal interconnect and underlying interconnect layers. This three-dimensional approach to capacitance formation avoids increasing planar footprint complexity while enhancing capacitance performance.
3Reliability
If two-terminal memory cells are integrated with optimized power mesh, then resistance characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The reservoir capacitors are formed as part of the interconnect structure during the metal layer formation process, before memory cell fabrication is completed. This preliminary action integrates the capacitance function into the power mesh structure early in the manufacturing sequence, simplifying subsequent processing steps for two-terminal memory cell integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves interconnect resistance characteristics and enables stable capacitance operation, enhancing the performance of two-terminal memory cells in variable resistive memory devices.
Implementation Method 1
A reservoir capacitor may be formed between the first and second uppermost metal interconnects which are alternately arranged
Data Source
AI summary
A variable resistive memory device may include a semiconductor substrate, a device layer, an upper metal interconnect, a plurality of memory cells, and an uppermost metal interconnect. The device layer may be formed on the semiconductor substrate including memory cell array regions, and may include a plurality of lower metal interconnect layers. The upper metal interconnect may be arranged on the device layer, and may include a plurality of metal patterns. The plurality of memory may be arranged over the device layer in which the upper metal interconnect is formed and are in contact with certain metal patterns selected from the metal patterns constituting the upper metal interconnect. The uppermost metal interconnect may be located over the plurality of memory cells, and may be in contact with other portion of the metal patterns constituting the upper metal interconnect.