Variable Resistive Memory Stepwise Voltage Control
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Solution Overview
Problem
Cross-point array type variable resistive memory devices face electrical issues due to transient currents generated during memory cell turn-on, leading to potential unintended reset states and write disturbances affecting operational reliability.
Innovation Solution
A variable resistive memory device with a memory cell array and control block that applies a minimum voltage difference between bit and word lines, using stepwise voltage increases on the bit line to reduce transient currents and stabilize memory cell operation, thereby minimizing snapback and overshoot currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage is applied to turn on a memory cell in a cross-point array type variable resistive memory device, then the memory cell can be accessed and written, but transient currents are generated causing snapback and overshoot effects that lead to unintended reset states and write disturbances
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a first voltage level before the write operation begins. This preliminary voltage application ensures that when the write voltage is subsequently applied, the voltage difference across the memory cell is controlled, preventing excessive transient currents while still enabling successful write operations. The preliminary action of setting up the voltage condition in advance resolves the contradiction between enabling memory access and preventing harmful transient effects.
2Reliability
If a high voltage is applied to the bit line to ensure successful write operation, then the write margin is improved, but transient currents increase causing more severe snapback and overshoot effects
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage level on the bit line based on the operational phase. During the pre-charge phase, the bit line is set to a first voltage level, and during the write phase, a controlled second voltage level is applied. This parameter change approach allows the system to achieve sufficient write margin while controlling the voltage difference to minimize snapback currents. The controlled parameter adjustment resolves the contradiction between achieving reliable writes and minimizing harmful transient effects.
3Stability of the object's composition
If the voltage on the bit line is increased stepwise after turn-on detection, then the memory cell remains stably turned on, but the complexity of the control circuit increases
Solution Approach 1:
The patent applies periodic action by implementing a two-stage voltage application sequence: first a pre-charge voltage level, then a write voltage level. This periodic or sequential voltage application ensures stable memory cell operation during the write process while using simple control logic that detects turn-on and transitions between voltage levels. The periodic voltage stages provide stability without requiring complex continuous control circuits, resolving the contradiction between stability and circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces transient currents and stabilizes voltage and current in selected memory cells, enhancing operational reliability by maintaining the memory cell in a stable state during write operations and preventing unintended reset states.
Implementation Method 1
The control block may apply a voltage between a bit line and a word line connected with the selected memory cell to form a minimum voltage difference for turning-on the selected memory cell
Implementation Method 2
The control block may stepwise increase the voltage applied to the bit line to a target voltage level when the selected memory cell is turned on
Data Source
AI summary
A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.