Variable Resistive Memory Write Control Circuit
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Solution Overview
Problem
Current multi-level variable resistive memory devices face challenges in accurately writing data values due to variations in resistance levels, leading to potential read errors and reduced data storage reliability.
Innovation Solution
A method and device that apply a write current to a variable resistive memory cell, verify its resistance against intended resistance windows, and adjust the current based on verification results to ensure accurate data storage, using a verification sense amplifier and write control circuit to manage the write current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed write current is applied to the variable resistive memory cell, then the writing process is simple and fast, but the resistance may not accurately fall within the intended resistance window due to variations, leading to read errors
Solution Approach 1:
The patent implements a feedback mechanism where the actual resistance of the memory cell is measured after applying write current, and this measurement is used to adjust subsequent write current applications. The controller compares the measured resistance against target resistance windows and iteratively adjusts the write current magnitude until the resistance falls within the desired range, thereby ensuring reliable data storage while maintaining a relatively simple overall system architecture.
2Manufacturing precision
If the write current is varied to achieve accurate resistance values, then data storage accuracy improves, but the writing time increases due to multiple verification and adjustment cycles
Solution Approach 1:
The patent applies partial action by initially using a larger write current to quickly bring the resistance close to the target range, then using smaller adjustment currents in subsequent iterations to fine-tune the resistance value. This approach reduces total writing time compared to using only small incremental adjustments, while still achieving the required precision. The controller adapts the current magnitude based on how far the current resistance is from the target window.
3Reliability
If multiple verification cycles are performed to ensure resistance is within the resistance window, then read errors are minimized, but the overall writing process becomes more complex and time-consuming
Solution Approach 1:
The patent employs dynamic verification where the number and nature of verification cycles adapt based on the current resistance state. The controller performs verification measurements after each write current application and adjusts subsequent actions based on whether the resistance is below, within, or above the target window. This dynamic approach ensures high data accuracy while avoiding unnecessary verification cycles, thereby maintaining better writing speed compared to fixed multi-cycle verification protocols.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of data writing by ensuring the resistance of the memory cell falls within specific resistance windows, minimizing read errors and improving data storage density and integrity.
Implementation Method 1
variable resistive memory cell to store data in a non-volatile manner... change in resistance of variable resistance materials
Implementation Method 2
verification sense amplifier verifying whether the actual resistance of the variable resistive memory cell resides in an intended resistance window
Data Source
AI summary
Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.