Variable-Resistor Analog MAC Arrays for Real-Time Computation
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Solution Overview
Problem
Conventional Multiply-Accumulator (MAC) circuits are complex, large, and inefficient in terms of chip area and power consumption, while analog synapse arrays with non-volatile memory cannot support real-time MAC computation due to static operand values, limiting computation capability and neural network efficiency.
Innovation Solution
Analog multiplier accumulator arrays are designed with variable resistors and transistors, allowing real-time computation by dynamically updating operand values without reprogramming, reducing transistor count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional digital MAC circuits are used, then computation capability is achieved, but chip area and power consumption are excessive
Solution Approach 1:
The patent replaces conventional digital logic circuits with analog circuit implementations. Specifically, it uses analog multipliers and accumulators that operate with continuous voltage signals instead of discrete digital logic gates, thereby reducing the physical area required while maintaining computation capability.
Solution Approach 2:
The patent changes the operating parameters from digital voltage levels (discrete 0 and 1) to analog voltage levels (continuous range), enabling more compact circuit implementations. The analog MAC unit processes multiple bits simultaneously through voltage multiplication and accumulation, reducing the number of transistors and logic gates needed.
2Reliability
If Flash memory is used for operand storage, then non-volatile storage is achieved, but real-time updating is prevented due to slow programming speed
Solution Approach 1:
The patent introduces dynamic reconfiguration capability to the analog MAC unit by incorporating switches (e.g., MOS transistors) that can rapidly change the resistance values of variable resistors during operation. This allows the stored operands to be updated in real-time without requiring Flash memory reprogramming, combining non-volatile storage with dynamic update capability.
Solution Approach 2:
The patent divides the operand storage into multiple variable resistors that can be independently controlled and updated. Each variable resistor can be adjusted separately through dedicated control circuits, enabling selective and rapid updates of specific operands without affecting the entire memory array.
3Reliability
If each digital logic signal uses full VDD-GND swing, then logic levels are well-defined, but power consumption increases
Solution Approach 1:
The patent changes the signal representation from full-swing digital logic levels to smaller analog voltage variations. The analog MAC unit processes information through subtle voltage changes that accumulate over multiple operations, reducing the energy required per switching event while maintaining sufficient signal integrity through careful circuit design.
4Reliability
If each wire carries only a single bit, then signal integrity is maintained, but data throughput is limited
Solution Approach 1:
The patent replaces the digital bit-by-bit processing approach with analog parallel processing. Multiple data values are represented simultaneously by voltage levels on the same wire, enabling multiple bits of information to be transmitted and processed in parallel through a single analog channel, thereby increasing data throughput while maintaining signal integrity through differential signaling and noise cancellation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient, real-time MAC operations with reduced chip area and power usage, supporting larger and deeper neural network models.
Implementation Method 1
an access transistor and a variable resistor forming an analog multiplier, the variable resistor modulating a current flow through the access transistor in response to an input voltage
Data Source
AI summary
An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.