Variable Resistor Memory Cell Adaptive Write Control
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face challenges in efficiently rewriting memory cells due to variations in rewrite time, making it difficult to determine the optimal rewrite conditions and shorten the cycle time, as the rewrite operation is often slowed by slower memory cells.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array using variable resistors, a voltage supply circuit, detection circuit, and output circuit that applies controlled voltages and detects resistance changes, allowing for real-time monitoring of memory cell states through flag data to adjust write times based on individual cell speeds, thereby optimizing the setting and resetting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant rewrite voltage is applied for a constant time on multiple occasions with verify operations, then all memory cells can be rewritten, but the rewrite time is determined by the slowest memory cells causing extended cycle time
Solution Approach 1:
The patent implements a feedback mechanism where the result of each verify operation is used to adjust the rewrite strategy. When verify detects that a memory cell has been successfully rewritten, the system stops applying rewrite voltage to that cell and continues only with cells that require further rewriting. This feedback-driven approach prevents unnecessary waiting for slow cells and reduces overall cycle time while ensuring all cells are properly rewritten.
Solution Approach 2:
The patent transforms the static rewrite process (constant voltage applied to all cells for fixed duration) into a dynamic process where rewrite voltage is selectively applied based on real-time verify results. The system adaptively adjusts which cells receive rewrite voltage in each cycle, optimizing the rewrite operation by focusing resources only on cells that need it, thereby reducing total cycle time while maintaining reliability.
2Ease of manufacture
If rewrite voltage is applied to all memory cells simultaneously for a fixed duration, then uniform processing is achieved, but individual cell speed variations cause inefficiency
Solution Approach 1:
The patent segments the memory cell population into groups based on their rewrite status, identified through verify operations. Instead of treating all cells uniformly, the system divides them into those that have been successfully rewritten and those that require further rewriting. This segmentation allows independent processing of different cell groups, enabling faster overall rewrite by avoiding the constraint imposed by the slowest cells.
Solution Approach 2:
The patent changes the processing parameters dynamically based on verify results. Rather than maintaining constant voltage and time parameters for all cells, the system adjusts the rewrite voltage application duration and intensity according to each cell's actual rewrite status. This parameter adaptation allows optimal rewrite speed for each cell while maintaining uniform processing quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and reliable data rewriting by allowing for real-time monitoring and adjustment of write operations, reducing unnecessary standby time and improving memory performance by matching write times with individual cell speeds, thus enhancing operational speed and reliability.
Implementation Method 1
each having a floating gate structure... resistive type memory which uses a variable resistor as the memory cell... in which resistance variation occurs due to presence/absence of a trapped charge in a charge trap existing at an electrode interface and ones in which resistance variation occurs due to presence/absence of a conductive path induced by oxygen deficiency or the like
Implementation Method 2
a detection circuit operative to detect change in a resistance state of the memory cells during application of the certain voltage to the memory cells
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information. An output circuit outputs to external at least a portion of the detection information outputted from the detection circuit.