Variable Resistor Memory Cell Contact Region Merging
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Solution Overview
Problem
The existing nonvolatile semiconductor memory devices with variable resistor elements face limitations in circuit integration due to the requirement of multiple contact regions for each memory cell, restricting the degree of integration and accessibility in the memory array.
Innovation Solution
A nonvolatile memory device is designed with a source selector transistor and a series of cell selector transistors connected to a variable resistor element, allowing the transistors to control the resistance change by applying a voltage stress between the bit line and the source line, reducing the need for additional contact regions and improving circuit integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory cell is formed by connecting the variable resistor element and the selector transistor with multiple contact regions, then the memory cell can be accessed properly, but the degree of integration is restricted due to the increased layout complexity
Solution Approach 1:
The patent merges the source contact region with the drain contact region of the selector transistor, so that one contact region serves dual purposes: connecting the source of the selector transistor and connecting the variable resistor element. This reduces the number of contact regions from four to three per memory cell, thereby reducing layout complexity while maintaining proper memory cell accessibility.
2Reliability
If four contact regions are provided for each memory cell to connect variable resistor element and selector transistor, then the memory cell structure is complete, but the area occupied increases and degree of integration is restricted
Solution Approach 1:
The patent combines the source contact region of the selector transistor with one of the contact regions of the variable resistor element. This merging eliminates the need for a separate contact region, reducing the total number of contact regions from four to three per memory cell, thereby reducing the area occupied by each memory cell and improving the degree of integration.
3Ease of operation
If the memory array is formed with multiple memory cells arranged in rows and columns, then random access is enabled, but the circuit layout becomes complex due to multiple word lines, bit lines and source lines
Solution Approach 1:
The patent merges the source line connection with the drain connection of the selector transistor, eliminating the need for separate source line connections to each memory cell. This reduces the number of wiring layers and simplifies the circuit layout while maintaining the random access capability through the row-column addressing scheme using word lines and bit lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables random access to variable resistor elements while enhancing the degree of integration in the memory array, reducing the area occupied by the device and maintaining low impedance across the memory cell structure.
Implementation Method 1
a variable resistor element which is constituted as a memory element to store bit information
Data Source
AI summary
A nonvolatile memory device is disclosed. The nonvolatile memory device includes a source selector transistor connected at one end thereof to a source line, a plurality of cell selector transistors connected in series with each other and to the other end of said source selector transistor and a basic memory unit including a variable resistor element which is constituted as a memory element to store bit information and is provided for each of said cell selector transistors, being connected at one end thereof to the drain terminal of said cell selector transistor and connected at the other end thereof to the bit line. The source selector transistor and said cell selector transistor provided between one end of said variable resistor element to be accessed and said source line are controlled to turn on.


