Variable Resistor Memory Erase Pulse Width Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In non-volatile semiconductor memory devices using variable resistors, the variation in wiring resistance along access paths to memory cells leads to inconsistent data write, erase, and read characteristics, causing issues such as re-programming during data erase operations due to uneven pulse application.
Innovation Solution
The memory device employs a controller to generate erase pulses with varying pulse widths based on the access path length to each memory cell, compensating for wiring resistance variations by adjusting the pulse width exponentially or in a stepwise manner to ensure consistent data erase operations across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed pulse width is used for data erase operations, then the control circuit is simple, but data erase characteristics vary among memory cells due to wiring resistance differences
Solution Approach 1:
The patent applies dynamics by making the pulse width adjustable rather than fixed. The control circuit dynamically determines the pulse width based on the access path length to each memory cell, allowing the system to adapt to varying wiring resistance conditions while maintaining reliable data erase operations across all memory cells.
Solution Approach 2:
The patent changes the parameter of pulse width according to the access path length. By varying the pulse width parameter based on the specific memory cell location and corresponding wiring resistance, the system compensates for resistance differences and ensures consistent data erase characteristics without requiring complex additional circuitry.
2Reliability
If the pulse width is increased to compensate for wiring resistance, then data erase characteristics improve, but re-programming occurs during data erase operations
Solution Approach 1:
The patent applies local quality by tailoring the pulse width to the specific access path length of each memory cell. Instead of using a uniformly increased pulse width that causes re-programming, the system assigns appropriate pulse widths locally based on each memory cell's position and wiring resistance, achieving consistent erase characteristics without harmful re-programming effects.
Solution Approach 2:
The control circuit incorporates feedback by determining the pulse width based on the access path length information. This feedback mechanism allows the system to adjust the pulse width appropriately for each memory cell, preventing both incomplete erase and re-programming by using just the right amount of pulse width for each location.
3Reliability
If a longer pulse is applied to compensate for voltage drop, then data can be erased in cells with high wiring resistance, but the resistance varying element may switch back to low-resistance state
Solution Approach 1:
The patent changes the pulse width parameter based on the access path length to compensate for voltage drop without causing re-programming. By calculating and applying the appropriate pulse width for each memory cell's specific wiring resistance, the system ensures reliable data erase while maintaining stability of the resistance state change.
Solution Approach 2:
The system dynamically adjusts the pulse width according to the specific memory cell location and wiring resistance conditions. This dynamic adjustment allows the control circuit to apply just enough pulse width to achieve reliable erase in high-resistance paths without exceeding the threshold that would cause the resistance varying element to switch back to the low-resistance state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses variations in data erase characteristics among memory cells, preventing re-programming and ensuring reliable data operations without increasing the risk of incomplete erase operations.
Implementation Method 1
a resistance varying memory using a variable resistor for a memory cell has been proposed as a technique to achieve further miniaturization of memory cells
Implementation Method 2
the wiring resistance in an access path to a memory cell is different from one memory cell to another, as in the case of the other non-volatile memories. This causes variation in data write/erase/read characteristics among the memory cells
Data Source
AI summary
A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.