Variable Resolution PWM Generation Using Divide-by-W Counter
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Solution Overview
Problem
Current microprocessor-based PWM systems face limitations in achieving high resolution due to timer interrupt latency, resulting in quasi-random timing errors that affect system performance, especially in high-response systems, and require costly hardware modifications for improved resolution.
Innovation Solution
A system comprising a microcontroller, a divide by W counter, a delay circuit, and a flip-flop with a logic gate to generate a PWM signal with variable duty cycle resolution, minimizing hardware usage and CPU overhead, allowing resolution up to a fraction of the CPU time period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If timer interrupt latency is used in software-based PWM generation, then CPU overhead is reduced, but timing precision and PWM resolution deteriorate due to quasi-random timing errors
Solution Approach 1:
The PWM generation function is segmented into two parts: a software component that sets the duty cycle ratio, and a hardware component (counter and logic gate) that generates the precise PWM waveform. This segmentation allows the CPU to avoid timing-critical operations while maintaining high resolution through hardware-based pulse generation.
Solution Approach 2:
A counter circuit serves as an intermediary between the CPU and the PWM output. The counter receives the duty cycle ratio from the CPU, then autonomously generates the PWM waveform using its internal clock and logic gates, eliminating the need for CPU intervention during the actual pulse generation process.
2Measurement precision
If hardware modifications are made to improve PWM resolution, then PWM resolution improves, but system cost and complexity increase
Solution Approach 1:
The counter circuit performs multiple functions: it acts as a frequency divider, a timing generator, and a waveform shaper. By using a single counter component with clock input and logic gate outputs, the system achieves high-resolution PWM without requiring multiple specialized hardware components.
Solution Approach 2:
Instead of modifying the CPU's internal timer hardware to achieve higher resolution, the invention creates a separate, dedicated counter circuit that copies the essential timing function but operates at higher resolution using its own clock source and logic gate structure.
3Measurement precision
If direct CPU control is used for each PWM output pulse, then PWM timing precision improves, but CPU time and productivity are reduced
Solution Approach 1:
The counter is pre-configured with the duty cycle ratio before PWM generation begins. This preliminary setup allows the counter to autonomously generate precise PWM waves without requiring CPU intervention during the actual pulse generation, thus maintaining timing precision while freeing CPU resources.
4Measurement precision
If PWM resolution is increased beyond input frequency multiples, then output resolution improves, but timer interrupt latency causes timing errors
Solution Approach 1:
The system dynamically adjusts the counter's operating parameters based on the desired PWM resolution. The counter can operate at different division ratios and clock frequencies to achieve various resolution levels without being constrained to fixed multiples of the input frequency, while maintaining timing accuracy through hardware-based generation.
Data Source
AI summary
A system and method generate a pulse width modulated signal having variable duty cycle resolution. A hardware uses minimal hardware to improve the PWM duty cycle resolution up to 0, such that highest possible resolution of a waveform can be obtained, including a sine wave. An embodiment of the invention uses a microcontroller, a divide by W counter, a delay circuit, a flip-flop, and a logic gate.