Variable Sampling Rate Transmitter for Clock Harmonic Mitigation
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Solution Overview
Problem
Full-duplex radio transceivers face significant signal degradation due to harmonic interference from clock signals, which are not efficiently mitigated by existing methods, particularly affecting the receiver's signal quality even at low harmonic amplitudes due to high gain in the RF components.
Innovation Solution
The method involves determining and selecting the frequency of clock signals related to analog-digital, digital-analog, and sample rate converters to ensure spurious tones fall outside the receiver bandwidth or align with subcarrier frequencies, using a controller and data tables to measure and mitigate these interferences, potentially switching between primary and secondary clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional space is designed between functional blocks to suppress clock harmonics, then interference mitigation is improved, but device area increases
Solution Approach 1:
The patent changes the clock signal frequency parameter to a variable sampling rate that is dynamically adjustable. By changing the clock frequency, the harmonic frequencies are shifted away from the receiver bandwidth, mitigating interference without requiring additional physical space. This resolves the contradiction by addressing the harmful factor through parameter modification rather than spatial separation.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment where the sampling rate can be changed based on operational conditions. This dynamic approach allows the system to adaptively mitigate harmonics by shifting their frequencies away from sensitive receiver bands, eliminating the need for fixed large spacing between functional blocks.
2Object-affected harmful factors
If decoupling capacitors or shunt circuits are used to separate interference sources, then clock harmonic suppression is improved, but device complexity and area increase
Solution Approach 1:
Instead of adding decoupling capacitors or shunt circuits, the patent changes the operational parameter (clock frequency) of the existing DAC to shift harmonics away from the receiver bandwidth. This parameter-based solution avoids increasing device complexity while achieving the same interference mitigation goal.
3Productivity
If clock frequency is increased to improve data conversion rate, then productivity is improved, but harmonic interference increases
Solution Approach 1:
The patent implements dynamic frequency selection where the clock frequency can be adjusted based on the operating mode. When high data conversion rate is needed, a higher frequency can be used, but when receiver sensitivity is critical, the frequency can be lowered or modulated to shift harmonics away from the receiver band, thus balancing productivity and interference.
Solution Approach 2:
By making the clock frequency a variable parameter rather than a fixed value, the system can optimize between data conversion rate and harmonic interference. The frequency can be changed to achieve the desired productivity while keeping harmonics outside the receiver bandwidth through careful frequency selection.
Data Source
AI summary
The present invention presents a method and a system for mitigating effects of clock harmonics in the receiver. The receiving signal may be monitored in such a way that the interfering harmonic component is tracked. When the interfering frequency is found out, the system determines the clock or clocks in the transceiver which are contributing to the interfering spurious tone. After that, the contributing clock(s) frequency is selected so that the effect of the spurious tone in the receiving passband is minimized or mitigated. This is performed by selecting a suitable clock frequency resulting in the spurious tones all falling outside the receiver passband; or in an OFDM system, by choosing a clock frequency deriving the spurious tone straight onto a subcarrier signal frequency.