Variable Sheet ForkFET Device for Weff Adjustment
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling nanosheet field effect transistors (FETs) below 40 nm while enabling dual work function metal (WFM) integration, as standard integration methods allow only one vertical sheet-to-sheet space across the wafer, limiting the adjustment of effective width (Weff) and gate stack thickness for different devices.
Innovation Solution
The proposed solution involves a forkFET structure with a first FET device and a second FET device separated by a vertical dielectric pillar, where the first FET has a greater number of horizontal sheet channels than the second FET, allowing for adjustable Weff and different gate dielectric thicknesses, enabling the formation of both logic and I/O devices on the same chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard integration methods are used, then manufacturing process is simple, but adjustment of effective width (Weff) and gate stack thickness for different devices is limited
Solution Approach 1:
The patent divides the semiconductor structure into separate regions (first region and second region) with different numbers of nanosheets, allowing independent adjustment of effective width for different devices. This segmentation enables customized device characteristics without requiring complete redesign of the entire integration scheme.
Solution Approach 2:
The patent implements local quality by having different regions with different numbers of nanosheets (e.g., first region with three nanosheets, second region with two nanosheets), allowing each region to be optimized for specific device requirements such as logic or I/O functions while maintaining a unified manufacturing process.
2Quantity of substance
If more horizontal sheet channels are used, then effective width (Weff) increases, but device leakage to substrate increases
Solution Approach 1:
The patent introduces a bottom dielectric isolation layer as an intermediary between the nanosheet channels and the substrate. This isolation layer effectively blocks leakage currents while allowing the beneficial effects of multiple nanosheets for increased effective width, thus resolving the contradiction between quantity of channels and leakage control.
3Length of moving object
If gate dielectric thickness is reduced, then device scaling is improved, but reliability and control of electrical properties deteriorate
Solution Approach 1:
The patent employs parameter changes by using different gate dielectric thicknesses in different regions of the device. Thinner gate dielectrics are used where scaling is critical, while thicker gate dielectrics are used where reliability and electrical control are paramount, allowing optimization of both contradictory requirements across the device structure.
Data Source
AI summary
An embodiment of the invention may include a forkFET semiconductor structure, and the method of forming said structure. The structure may include a first FET device and a second FET device separated by a vertical dielectric pillar. The first FET device may include a first plurality of horizontal sheet channels. The second FET device may include a second plurality of horizontal sheet channels. The first plurality of horizontal sheet channels contains more horizontal sheets than the second plurality of horizontal sheet channels. This may enable adjustment of Weff for different devices on different sides of the pillar or different thicknesses of dielectrics used for the device.