Variable-Size Flash Translation Layer for SSD Storage Efficiency
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Solution Overview
Problem
Conventional solid state drives face storage efficiency issues due to fixed, integer-sized host logical blocks in nonvolatile memory, which do not accommodate variable user data sizes, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A variable-size flash translation layer method that reads and maps logical block addresses to physical addresses, allowing for variable-sized data storage and retrieval by converting information into addresses and number of read units within memory pages, and using headers to locate and extract data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed, integer number of host logical blocks are stored in each page of nonvolatile memory, then the storage structure is simple and hardware requirements are reduced, but storage efficiency deteriorates when user data size or usable page size is not fixed
Solution Approach 1:
The patent implements a variable-size flash translation layer that dynamically adjusts the number of logical blocks per page based on actual data size requirements. Instead of using a fixed integer number of logical blocks per page, the system varies the block count to match the actual data being stored, thereby improving storage efficiency while maintaining a relatively simple storage structure through software-based management.
2Productivity
If variable size flash translation layer is implemented to support variable user data sizes, then storage efficiency and adaptability improve, but hardware complexity increases
Solution Approach 1:
The patent introduces a flash translation layer as an intermediary software component that sits between the host and the nonvolatile memory. This translation layer handles the complexity of variable-size data mapping, logical block address translation, and page management, thereby enabling variable data size support without requiring complex hardware modifications. The FTL acts as a mediator that absorbs the hardware complexity burden.
3Measurement precision
If page headers are used to identify user data location among multiple read units, then data location accuracy improves, but read operation complexity and time increase due to required header parsing
Solution Approach 1:
The patent implements a translation layer that performs preliminary actions by pre-calculating and storing the mapping between logical block addresses and physical page locations in a translation table. When a read operation is needed, the system can quickly retrieve the pre-computed location information rather than parsing page headers in real-time, thereby maintaining accurate data location while reducing read operation time.
Data Source
AI summary
A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.