Variable Size Logical Registers for Graph Stream Processing
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Solution Overview
Problem
In graph stream processing systems, the fixed register width leads to inefficiency as it cannot accommodate different data types efficiently, resulting in either multiple clock cycles for loading or the need for wide registers to handle the largest data type, limiting throughput in compute-intensive applications.
Innovation Solution
A system and method that utilize Single Instruction Multiple Data (SIMD) threads with a dispatch mask, where a thread scheduler initiates SIMD threads, and an instruction iterator determines the data type and number of clock phases required for execution, using a Content Addressable Memory (CAM) to map logical registers to physical registers, allowing for efficient management of different data types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the register width is fixed to handle the largest data type, then all data types can be accommodated, but the system efficiency deteriorates due to unnecessary use of wider registers for smaller data types
Solution Approach 1:
The patent implements variable register widths that can be dynamically adjusted based on the data type being processed. The register file contains multiple banks with different widths (e.g., 8-bit, 16-bit, 32-bit, 64-bit), and the system selectively activates appropriate register widths using control signals. This dynamic adaptation allows the system to match register width to data type requirements, avoiding the inefficiency of always using the widest register width while maintaining the ability to handle all data types.
2Adaptability or versatility
If multiple clock cycles are used to load registers for different data types, then all data types can be processed, but the throughput decreases due to increased execution time
Solution Approach 1:
The patent segments the register file into multiple independent banks, each with a specific width (e.g., 8-bit bank, 16-bit bank, 32-bit bank, 64-bit bank). Each bank can be independently accessed and loaded in a single clock cycle. The system uses control signals to select the appropriate bank based on the data type requirement, enabling single-cycle loading for each data type while maintaining support for all data types through the segmented bank structure.
3Ease of operation
If wide registers are used to hold the largest data type, then all data types fit in one register, but the precision and efficiency deteriorate due to unused register bits
Solution Approach 1:
The patent applies local quality by providing different register widths in different banks according to the specific data type requirements. Each bank is optimized for its specific width, ensuring that register bits are fully utilized without waste. For example, 8-bit data uses the 8-bit bank with all bits actively used, while 64-bit data uses the 64-bit bank. This localized optimization ensures both ease of operation and processing precision by matching register capacity exactly to data requirements.
Data Source
AI summary
Systems, apparatuses and methods are disclosed for efficient management of registers in a graph stream processing (GSP) system. The GSP system includes a thread scheduler module operative to initiate a Single Instruction Multiple Data (SIMD) thread, the SIMD thread including a dispatch mask with an initial value. A thread arbiter module operative to select an instruction from the instructions and provide the instruction to each of one or more compute resources, and an instruction iterator module, associated with the each of one or more compute resources operative to determine a data type of the instruction. The instruction iterator module iteratively executes the instruction based on the data type and the dispatch mask.