Variable-Size Packet Processing Pipelines for Network Hardware Efficiency
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Solution Overview
Problem
Current packet processing hardware is inefficient due to the need for parallel units to handle maximum-size packets, leading to wasteful resource usage and high power consumption, as multiple packets often share a data bus, requiring redundant data handling and extensive logic resources.
Innovation Solution
A network packet processor with multiple processing pipelines of varying sizes, each capable of processing packets up to a specific size, and a scheduling circuit that assigns packets based on their sizes, optimizing hardware usage by reducing the processing size of each pipeline and minimizing redundant data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple identical packet processing hardware instances are used to handle maximum-size packets, then throughput is maintained, but hardware resources and power consumption increase significantly
Solution Approach 1:
Different processing pipelines are configured with different processing sizes tailored to their specific packet size requirements. The first processing pipeline has a first processing size and the second processing pipeline has a second processing size, allowing each pipeline to be optimized for its specific workload rather than all pipelines being over-engineered for maximum-size packets
Solution Approach 2:
The packet processing system is divided into multiple processing pipelines, each handling packets of specific sizes. The scheduling circuit divides packets into different groups based on size, and each pipeline processes only the packets it is configured for, reducing redundant hardware in each pipeline
2Reliability
If all packet processing units are configured to handle maximum-size packets, then worst-case scenarios are covered, but redundant data handling and logic resources are wasted
Solution Approach 1:
Each processing pipeline is configured with a specific processing size appropriate to its function. The first processing pipeline handles packets up to a first processing size while the second processing pipeline handles packets up to a second processing size, eliminating the need for all pipelines to be over-engineered for maximum-size packets
Solution Approach 2:
Instead of configuring all pipelines to handle the maximum possible packet size (excessive action), each pipeline is configured to handle only the packet sizes it actually needs to process (partial action), reducing unnecessary hardware resources and power consumption
3Productivity
If the data path is fanned-out into k independent hardware pipelines, then packet processing capacity increases, but routing resources and power consumption increase due to redundant data transmission
Solution Approach 1:
Multiple processing pipelines share common routing resources and data paths rather than having completely independent pipelines. The scheduling circuit efficiently routes packets to appropriate pipelines, and pipelines can share common infrastructure for packet extraction and processing, reducing redundant routing resources
Data Source
AI summary
A network packet processor includes a plurality of processing pipelines and a scheduling circuit. Each processing pipeline is configured and arranged to process packets having sizes less than or equal to an associated processing size of the processing pipeline. The respective processing size of one of the processing pipelines is different from the processing size of at least one other of the processing pipelines. The scheduling circuit is coupled to the plurality of processing pipelines and is configured and arranged to determine respective packet sizes of packets input from a bus. The scheduling circuit assigns each packet of the one or more packets for processing by one of the processing pipelines as a function of the respective packet size of the packet and the processing size associated with the one of the processing pipelines.